Re: error in verilog?

On 2/26/16 4:36 AM, Mr C Camacho wrote:
> If (probably by using MyHDL incorrectly) yosys reports a syntax
> error with generated verilog, is this a bug with MyHDL (shouldn't
> MyHDL be reporting my idiocy)

If your testbench passes and the converted Verilog
fails then it is something worth looking at to see
if a bug exists.  Your best bet to getting working
converted V* is to test the MyHDL code.

>
> being as I have no idea what I'm doing or what the error is, I'd
> struggle to reproduce it in a minimal case, but it is just a
> Makefile and a couple of python scripts...
>
> this verilog
>
> 0 <= 1'b0;

You might have forgotten the ".next" in an assignment.

Regards,
Chris


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