error in verilog?

If (probably by using MyHDL incorrectly) yosys reports a syntax error 
with generated verilog, is this a bug with MyHDL (shouldn't MyHDL be 
reporting my idiocy)

being as I have no idea what I'm doing or what the error is, I'd 
struggle to reproduce it in a minimal case, but it is just a Makefile 
and a couple of python scripts...

this verilog

         0 <= 1'b0;

is where the error is happening

but I'm doing something dumb obviously because earlier

input [7:0] LEDS;

I'm attempting (probably incorrectly) to pass a top level output to a 
module where its manipulated

although the scripts are small I've not attached them as this usually 
triggers netiquette SJW's for some reason and I just can't be bothered.....



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