Re: JPEG Encoder and Leros Processor core (GSoC)

Radhika <[email protected]> Tue, 1 Mar 2016 12:30:45 +0530
Newsgroups gmane.comp.python.myhdl
Message-ID <CAOP8pGLir1EKgqEtbgbtgPis80551Q33Z7_iKVxX2DC_eYMGKg@mail.gmail.com>
Ah, no problem. Would it still be alright to ask proposal-related questions
about the Leros processor project here?

Radhika

On Tue, Mar 1, 2016 at 2:07 AM, Christopher Felton <[email protected]>
wrote:

> On 2/29/2016 1:41 PM, Radhika wrote:
> > Hi,
> >
> > I'm interested in contributing to MyHDL and I'm familiar with both
> > Verilog and Python. I'd love to implement either the JPEG Encoder
> > core or the Leros processor over the summer.
>
> Radhika,
>
> We have had quite a few students inquire about
> GSoC this year.  Right now we have about all the
> students we can handle.
>
> You are still welcome to create a proposal but if
> competing proposals are of similar quality preference
> will be given to the fist set of students.
>
> Regards,
> Chris
>
>
>
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