GSoC'16 | JPEG Encoder
Akshit Kumar <[email protected]> Wed, 2 Mar 2016 14:56:49 +0530
| Newsgroups | gmane.comp.python.myhdl |
|---|---|
| Message-ID | <CAGYVn7i5U3yO-UNxtQexPXgSFhKS1yF+XWTKi7mRFqkHr-eh-w@mail.gmail.com> |
Hi, My name is Akshit Kumar. I am a second year undergraduate student in the department of Electrical Engineering in Indian Institute of Technology, Madras. I wish to do a project under MyHDL in GSoC'16. After going through the projects list, I found the JPEG Encoder interesting, mainly because I know a bit of Verilog and basic scripting in Python. The description of the idea mentioned that familiarity with digital circuits - wanted to know to what extent,could someone give an example of the same. I am new to this, so could someone please help me getting started. Could someone tell me what specific pre-requisites do I need to have to get started with this project? -- Regards *Akshit Kumar* Second Year Undergraduate Student Department of Electrical Engineering Indian Institute of Technology, Madras http://akshitk.com ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ myhdl-list mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/myhdl-list