Re: GSoC'16 | JPEG Encoder

Hi,
Le 02/03/2016 15:09, Henry Gomersall a écrit :
> On 02/03/16 13:59, Henry Gomersall wrote:
>> E.g. when the DSP has to be pipelined to maximize throughput, it's no
>> longer just a multiplier and the code has to reflect that. You could
>> create a multiplier block with pipeline stages incorporated, but then
>> you're more or less doing as I suggest (and still with no guarantees the
>> synthesizer will do the right thing).
> I wrote an inline complex multiplier based around a single DSP which
> really gets into the guts of the DSP core. It's hard to see how one
> would do this in plain VHDL with a hope that it would be inferred
> correctly (the difficulty is in things like flicking control registers
> mid pipeline from multiply-add to multiply-accumulate to
> multiply-deccumulate).
I have discovered MyHDL recently and considering using it.
I have followed your discussion and get questions :
- How is it possible to "switch" the underlying resources  ("inner 
primitive blocks can be switched") ?
- Why do you say you can do things with MyHDL but not VHDL (your complex 
multiplier) ?

Nicolas
>
> Cheers,
>
> Henry
>
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