Dual port ram, mixed width byte enables.

Hi MyHDLs,
Is there a way to implement a dual port ram with mixed width ports and or
byte enables?

The template to infer one with Altera tools is something like this in VHDL:

architecture rtl of mixed_width_true_dual_port_ram is
constant RATIO       : natural := 2 ** (ADDRESS_WIDTH1 - ADDRESS_WIDTH2) ;
constant DATA_WIDTH2 : natural := DATA_WIDTH1 * RATIO;
constant RAM_DEPTH   : natural := 2 ** ADDRESS_WIDTH2;

-- Use a multidimensional array to model mixed-width
type word_t is array(RATIO - 1 downto 0) of std_logic_vector(DATA_WIDTH1 -
1 downto 0);
type ram_t is array (0 to RAM_DEPTH - 1) of word_t;

-- declare the RAM
signal ram : ram_t;

signal w1_local : word_t;
signal q1_local : word_t;

begin  -- rtl
-- Re-organize the write data to match the RAM word type
unpack: for i in 0 to RATIO - 1 generate
w1_local(i) <= data_in2(DATA_WIDTH1*(i+1) - 1 downto DATA_WIDTH1*i);
data_out2(DATA_WIDTH1*(i+1) - 1 downto DATA_WIDTH1*i) <= q1_local(i);
end generate unpack;

--port A
process(clk)
begin
if(rising_edge(clk)) then
if(we2 = '1') then
ram(addr2) <= w1_local;
end if;
q1_local <= ram(addr2);
end if;
end process;

-- port B
process(clk)
begin
if(rising_edge(clk)) then
data_out1 <= ram(addr1 / RATIO )(addr1 mod RATIO);
if(we1 ='1') then
ram(addr1 / RATIO)(addr1 mod RATIO) <= data_in1;
end if;
end if;
end process;
end rtl;


Greetings,
 Samuele

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