Re: Inconsistency between simulation and conversion

On 4/28/16 1:54 AM, Nicolas Pinault wrote:
> Hi,
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51: Â Â Â  Not
> supported: Augmented signal assignment
>
> This makes sense. However, this same statement does not trig any
> error when simulating the design. Is this the intended behaviour ?

I believe it is expected, only a subset is convertible.
You would not want to error on non-convertible statements
because they could be useful for modeling and test
(i.e. non-conversion).

The manual doesn't state one way or the other for signal
assignments, we should add that the *augmented* assignment
operators are not supported for signal assignments:
http://docs.myhdl.org/en/stable/manual/conversion.html#signal-assignment

Regards,
Chris




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