Support for port mapping during conversion to Verilog and some general doubts

      
          Dear myHDL Admin/ users,




Is 'port mapping' facility available in myHDL? When I tried creating
 instances of blocks it was making multiple copies of the full block 
with different names for variables.Where can I get the latest manual for myHDL? Is the one given in http://old.myhdl.org/doku.php/doc:pdf the latest one?


Thanks

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