Re: Support for port mapping during conversion to Verilog and some general doubts

Hi,
This is the development version http://docs.myhdl.org/en/latest/.
You should start from here because 1.0 is not so far from being tagged and
it will break compatibility with old code. See
http://docs.myhdl.org/en/latest/whatsnew/1.0.html.

On Sun, May 29, 2016 at 9:29 AM, Vineesh V S <[email protected]> wrote:

> Dear myHDL Admin/ users,
>
>
>
>    1. Is 'port mapping' facility available in myHDL? When I tried
>    creating instances of blocks it was making multiple copies of the full
>    block with different names for variables.
>    2. Where can I get the latest manual for myHDL? Is the one given in
>    http://old.myhdl.org/doku.php/doc:pdf the latest one?
>
>
> Thanks
>
>
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------------------------------------------------------------------------------
What NetFlow Analyzer can do for you? Monitors network bandwidth and traffic
patterns at an interface-level. Reveals which users, apps, and protocols are 
consuming the most bandwidth. Provides multi-vendor support for NetFlow, 
J-Flow, sFlow and other flows. Make informed decisions using capacity 
planning reports. https://ad.doubleclick.net/ddm/clk/305295220;132659582;e

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