Re: BUG: non-fixed-length ISAs are unsupported for now

>
> >> But Zilog eZ80 CPU has instructions up to 6 bytes long: like ld.il
> bc,(Mmn)
> >> (lil/sil prefix 0xed prefix <opcode> <n> <m> <M>) .
> >
> > You don't have to include pure operands in those 6.  Just the
> > opcode-containing bytes that tell cgen-level instructions apart.
>
> Yeah, just make sure that every (f-FOO CST) expression in instruction
> formats (+ ... ) are contained in the base-insn.
>
> Instruction operands can appear beyond the base insn without problems.



Ok. How to handle variable size instructions then? For example:
NOP - 0x00
NEG - 0xed 0x44
RLC B - 0xcb 0x00
LD HL, 0x1234 - 0x21 0x34 0x12
LD IY, 0x1234 - 0xfd 0x21 0x34 0x12
LD DE, (0x1234) - 0xed 0x5b 0x34 0x12
RR (IX+9) - 0xdd 0xcb 0x09 0x1e (here 0x09 is 8-bit signed immediate)