Re: [comedi] Comedi Driver with LPCIe-7250 problem

Ian Abbott <[email protected]> Thu, 29 May 2025 20:11:09 +0100
Newsgroups gmane.linux.comedi
Organization MEV Ltd.
Message-ID <[email protected]>
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On 29/05/2025 13:45, Ian Abbott wrote:
> On 2025-05-29 12:08, Gus Cerda wrote:
>> This is the information requested:
>>
>> */41:00.0 1100: 144a:7250 (rev 01)
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Subsystem: 144a:7000
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Flags: fast devsel, IRQ 242, IOMMU group 56
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92002000 (32-bit, non-prefetchable=
) [size=3D256]
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92001000 (32-bit, non-prefetchable=
) [size=3D256]
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92000000 (32-bit, non-prefetchable=
) [size=3D256]
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Capabilities: <access denied>
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel driver in use: adl_pci7250
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel modules: adl_pci7250/*
>
> OK, one change is that all three PCI BARs (0, 1, and 2) are using=20
> memory mapped I/O, but the driver is assuming that BAR 2 (the one that=20
> contained the DIO registers) uses port I/O. There might be other=20
> changes to the register layout.
>
> Looking at the Windows driver .INF file, I can see that this new=20
> card's details where added during the last 10 years, and is tied=20
> specifically to the LPCIe-7250. That .INF file shows that previous=20
> iterations of the PCI-7250 family used the following IDs:
>
> 10b5:9050 subsystem 9999:7250 (very early, using PLX's vendor and=20
> device ID and a dubious looking subvendor ID 0x9999)
> 144a:7250 subsystem 9999:7250 (newer, using ADLINK's vendor ID, but=20
> still using a dodgy subvendor ID)
> 144a:7250 subsystem 144a:7250 (probably the newest, before the=20
> redesigned LPCIe-7250)
>
> The Comedi driver will need changing to support the redesigned=20
> LPCIe-7250, once we've figured out the register layout.

I have implemented an experimental change to try and support the newer=20
LPCIe-7250 on branch wip-adl_pci7250-updates of the comedi git repository.

For now, I have assumed the registers are still in PCI BAR 2 and have=20
the same layout as the older cards. The change detects whether PCI BAR 2=20
is port I/O based or memory based, maps memory based registers to=20
virtual address space, and uses either the port I/O register access=20
functions or the memory-mapped I/O register access functions depending=20
on the type of registers.

It also limits the number of channels to 8 if the PCI subsystem device=20
ID is 0x7000 (which is used by the newer LPCIe-7250 cards), since it=20
cannot possibly have any PCI-7251 extension cards fitted to increase the=20
number of channels in that case.

The assumptions I made about the PCI BAR and register layout may not be=20
accurate, so please test and report your findings.

--=20
-=3D( Ian Abbott<[email protected]> || MEV Ltd. is a company  )=3D-
-=3D( registered in England & Wales.  Regd. number: 02862268.  )=3D-
-=3D( Regd. addr.: S11 & 12 Building 67, Europa Business Park, )=3D-
-=3D( Bird Hall Lane, STOCKPORT, SK3 0XA, UK. ||www.mev.co.uk )=3D-

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    <div class=3D"moz-cite-prefix">On 29/05/2025 13:45, Ian Abbott wrote:<b=
r>
    </div>
    <blockquote type=3D"cite"
      cite=3D"mid:[email protected]">
      <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3DUTF=
-8">
      <div class=3D"moz-cite-prefix">On 2025-05-29 12:08, Gus Cerda wrote:<=
br>
      </div>
      <blockquote type=3D"cite"
cite=3D"mid:[email protected]">
        <meta http-equiv=3D"content-type"
          content=3D"text/html; charset=3DUTF-8">
        This is the information requested:
        <div><br>
        </div>
        <div><b><i>41:00.0 1100: 144a:7250 (rev 01)<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Subsystem: 144a:7000<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Flags: fast devsel, IRQ 242, IOMM=
U group 56<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92002000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92001000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92000000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Capabilities: &lt;access denied&g=
t;<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel driver in use: adl_pci7250=
<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel modules: adl_pci7250</i></=
b><br>
        </div>
      </blockquote>
      <br>
      OK, one change is that all three PCI BARs (0, 1, and 2) are using
      memory mapped I/O, but the driver is assuming that BAR 2 (the one
      that contained the DIO registers) uses port I/O. There might be
      other changes to the register layout.<br>
      <br>
      Looking at the Windows driver .INF file, I can see that this new
      card's details where added during the last 10 years, and is tied
      specifically to the LPCIe-7250. That .INF file shows that previous
      iterations of the PCI-7250 family used the following IDs:<br>
      <br>
      10b5:9050 subsystem 9999:7250 (very early, using PLX's vendor and
      device ID and a dubious looking subvendor ID 0x9999)<br>
      144a:7250 subsystem 9999:7250 (newer, using ADLINK's vendor ID,
      but still using a dodgy subvendor ID)<br>
      144a:7250 subsystem 144a:7250 (probably the newest, before the
      redesigned LPCIe-7250)<br>
      <br>
      The Comedi driver will need changing to support the redesigned
      LPCIe-7250, once we've figured out the register layout.</blockquote>
    <p>I have implemented an experimental change to try and support the
      newer LPCIe-7250 on branch <font face=3D"monospace">wip-adl_pci7250-u=
pdates</font>
      of the comedi git repository.</p>
    <p>For now, I have assumed the registers are still in PCI BAR 2 and
      have the same layout as the older cards. The change detects
      whether PCI BAR 2 is port I/O based or memory based, maps memory
      based registers to virtual address space, and uses either the port
      I/O register access functions or the memory-mapped I/O register
      access functions depending on the type of registers.</p>
    <p>It also limits the number of channels to 8 if the PCI subsystem
      device ID is 0x7000 (which is used by the newer LPCIe-7250 cards),
      since it cannot possibly have any PCI-7251 extension cards fitted
      to increase the number of channels in that case.<br>
    </p>
    <pre class=3D"moz-signature" cols=3D"72"></pre>
    <p></p>
    <p>The assumptions I made about the PCI BAR and register layout may
      not be accurate, so please test and report your findings.</p>
    <pre class=3D"moz-signature" cols=3D"72">--=20
-=3D( Ian Abbott <a class=3D"moz-txt-link-rfc2396E" href=3D"mailto:abbotti@=
mev.co.uk">&lt;[email protected]&gt;</a> || MEV Ltd. is a company  )=3D-
-=3D( registered in England &amp; Wales.  Regd. number: 02862268.  )=3D-
-=3D( Regd. addr.: S11 &amp; 12 Building 67, Europa Business Park, )=3D-
-=3D( Bird Hall Lane, STOCKPORT, SK3 0XA, UK. || <a class=3D"moz-txt-link-a=
bbreviated" href=3D"http://www.mev.co.uk">www.mev.co.uk</a> )=3D-</pre>
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<p></p>

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