Re: [comedi] Comedi Driver with LPCIe-7250 problem

Gus Cerda <[email protected]> Fri, 30 May 2025 04:56:24 -0700 (PDT)
Newsgroups gmane.linux.comedi
Message-ID <[email protected]>
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I can't test the card today, I will try to test it on monday.=20
Have a good weekend!!
Thank you for all your effort.

El jueves, 29 de mayo de 2025 a las 21:11:15 UTC+2, Ian Abbott escribi=C3=
=B3:

> On 29/05/2025 13:45, Ian Abbott wrote:
>
> On 2025-05-29 12:08, Gus Cerda wrote:
>
> This is the information requested:=20
>
>
>
>
>
>
>
>
>
> *41:00.0 1100: 144a:7250 (rev 01)         Subsystem: 144a:7000        =20
> Flags: fast devsel, IRQ 242, IOMMU group 56         Memory at 92002000=20
> (32-bit, non-prefetchable) [size=3D256]         Memory at 92001000 (32-bi=
t,=20
> non-prefetchable) [size=3D256]         Memory at 92000000 (32-bit,=20
> non-prefetchable) [size=3D256]         Capabilities: <access denied>     =
   =20
> Kernel driver in use: adl_pci7250         Kernel modules: adl_pci7250*
>
>
> OK, one change is that all three PCI BARs (0, 1, and 2) are using memory=
=20
> mapped I/O, but the driver is assuming that BAR 2 (the one that contained=
=20
> the DIO registers) uses port I/O. There might be other changes to the=20
> register layout.
>
> Looking at the Windows driver .INF file, I can see that this new card's=
=20
> details where added during the last 10 years, and is tied specifically to=
=20
> the LPCIe-7250. That .INF file shows that previous iterations of the=20
> PCI-7250 family used the following IDs:
>
> 10b5:9050 subsystem 9999:7250 (very early, using PLX's vendor and device=
=20
> ID and a dubious looking subvendor ID 0x9999)
> 144a:7250 subsystem 9999:7250 (newer, using ADLINK's vendor ID, but still=
=20
> using a dodgy subvendor ID)
> 144a:7250 subsystem 144a:7250 (probably the newest, before the redesigned=
=20
> LPCIe-7250)
>
> The Comedi driver will need changing to support the redesigned LPCIe-7250=
,=20
> once we've figured out the register layout.
>
> I have implemented an experimental change to try and support the newer=20
> LPCIe-7250 on branch wip-adl_pci7250-updates of the comedi git repository=
.
>
> For now, I have assumed the registers are still in PCI BAR 2 and have the=
=20
> same layout as the older cards. The change detects whether PCI BAR 2 is=
=20
> port I/O based or memory based, maps memory based registers to virtual=20
> address space, and uses either the port I/O register access functions or=
=20
> the memory-mapped I/O register access functions depending on the type of=
=20
> registers.
>
> It also limits the number of channels to 8 if the PCI subsystem device ID=
=20
> is 0x7000 (which is used by the newer LPCIe-7250 cards), since it cannot=
=20
> possibly have any PCI-7251 extension cards fitted to increase the number =
of=20
> channels in that case.
>
> The assumptions I made about the PCI BAR and register layout may not be=
=20
> accurate, so please test and report your findings.
>
> --=20
> -=3D( Ian Abbott <[email protected]> || MEV Ltd. is a company  )=3D-
> -=3D( registered in England & Wales.  Regd. number: 02862268.  )=3D-
> -=3D( Regd. addr.: S11 & 12 Building 67, Europa Business Park, )=3D-
> -=3D( Bird Hall Lane, STOCKPORT, SK3 0XA, UK. || www.mev.co.uk )=3D-
>
>

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<div>I can't test the card today, I will try to test it on monday.=C2=A0</d=
iv><div>Have a good weekend!!</div><div>Thank you for all your effort.<br /=
><br /></div><div class=3D"gmail_quote"><div dir=3D"auto" class=3D"gmail_at=
tr">El jueves, 29 de mayo de 2025 a las 21:11:15 UTC+2, Ian Abbott escribi=
=C3=B3:<br/></div><blockquote class=3D"gmail_quote" style=3D"margin: 0 0 0 =
0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><div>
    <div>On 29/05/2025 13:45, Ian Abbott wrote:<br>
    </div>
    <blockquote type=3D"cite">
     =20
      <div>On 2025-05-29 12:08, Gus Cerda wrote:<br>
      </div>
      <blockquote type=3D"cite">
       =20
        This is the information requested:
        <div><br>
        </div>
        <div><b><i>41:00.0 1100: 144a:7250 (rev 01)<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Subsystem: 144a:7000<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Flags: fast devsel, IRQ 242, IOMM=
U group 56<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92002000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92001000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Memory at 92000000 (32-bit, non-p=
refetchable)
              [size=3D256]<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Capabilities: &lt;access denied&g=
t;<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel driver in use: adl_pci7250=
<br>
              =C2=A0 =C2=A0 =C2=A0 =C2=A0 Kernel modules: adl_pci7250</i></=
b><br>
        </div>
      </blockquote>
      <br>
      OK, one change is that all three PCI BARs (0, 1, and 2) are using
      memory mapped I/O, but the driver is assuming that BAR 2 (the one
      that contained the DIO registers) uses port I/O. There might be
      other changes to the register layout.<br>
      <br>
      Looking at the Windows driver .INF file, I can see that this new
      card&#39;s details where added during the last 10 years, and is tied
      specifically to the LPCIe-7250. That .INF file shows that previous
      iterations of the PCI-7250 family used the following IDs:<br>
      <br>
      10b5:9050 subsystem 9999:7250 (very early, using PLX&#39;s vendor and
      device ID and a dubious looking subvendor ID 0x9999)<br>
      144a:7250 subsystem 9999:7250 (newer, using ADLINK&#39;s vendor ID,
      but still using a dodgy subvendor ID)<br>
      144a:7250 subsystem 144a:7250 (probably the newest, before the
      redesigned LPCIe-7250)<br>
      <br>
      The Comedi driver will need changing to support the redesigned
      LPCIe-7250, once we&#39;ve figured out the register layout.</blockquo=
te>
    </div><div><p>I have implemented an experimental change to try and supp=
ort the
      newer LPCIe-7250 on branch <font face=3D"monospace">wip-adl_pci7250-u=
pdates</font>
      of the comedi git repository.</p>
    <p>For now, I have assumed the registers are still in PCI BAR 2 and
      have the same layout as the older cards. The change detects
      whether PCI BAR 2 is port I/O based or memory based, maps memory
      based registers to virtual address space, and uses either the port
      I/O register access functions or the memory-mapped I/O register
      access functions depending on the type of registers.</p>
    <p>It also limits the number of channels to 8 if the PCI subsystem
      device ID is 0x7000 (which is used by the newer LPCIe-7250 cards),
      since it cannot possibly have any PCI-7251 extension cards fitted
      to increase the number of channels in that case.<br>
    </p>
    <pre cols=3D"72"></pre>
    <p></p>
    <p>The assumptions I made about the PCI BAR and register layout may
      not be accurate, so please test and report your findings.</p></div><d=
iv>
    <pre cols=3D"72">--=20
-=3D( Ian Abbott <a href data-email-masked rel=3D"nofollow">&lt;abb...@mev.=
co.uk&gt;</a> || MEV Ltd. is a company  )=3D-
-=3D( registered in England &amp; Wales.  Regd. number: 02862268.  )=3D-
-=3D( Regd. addr.: S11 &amp; 12 Building 67, Europa Business Park, )=3D-
-=3D( Bird Hall Lane, STOCKPORT, SK3 0XA, UK. || <a href=3D"http://www.mev.=
co.uk" target=3D"_blank" rel=3D"nofollow" data-saferedirecturl=3D"https://w=
ww.google.com/url?hl=3Des&amp;q=3Dhttp://www.mev.co.uk&amp;source=3Dgmail&a=
mp;ust=3D1748692112576000&amp;usg=3DAOvVaw28yErLb303QTncYpPoB5mO">www.mev.c=
o.uk</a> )=3D-</pre>
  </div></blockquote></div>

<p></p>

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