Re: Support for TNT5002

Hi Dave,

> -----Original Message-----
> From: Daniel Sangorrin [mailto:[email protected]]
> Sent: Thursday, September 07, 2017 3:46 PM
> To: 'dave penkler'
> Cc: '[email protected]'; 'Ansgar Kueckes'
> Subject: RE: [Linux-gpib-general] Support for TNT5002
> 
> Hi Dave,
> 
> Thanks for your reply.
> 
> > -----Original Message-----
> > From: dave penkler [mailto:[email protected]]
> > Sent: Thursday, September 07, 2017 3:27 PM
> > To: Daniel Sangorrin
> > Cc: [email protected]; Ansgar Kueckes
> > Subject: Re: [Linux-gpib-general] Support for TNT5002
> >
> >
> >
> > On Thu, Sep 7, 2017 at 3:08 AM, Daniel Sangorrin <[email protected] <mailto:[email protected]> > wrote:
> >
> >
> > 	Dave, Ansgar:
> >
> >
> > 	Just for curiosity:
> >
> > 	I was confused because the manual (page 27, Register groups in PCI4882 Mode)
> > 	says that the 4882 register set is located at a 0x100~0x11F offset from PBAR1.
> > 	However, if you look at the driver source, accesses to the 4882 register set
> > 	occurs without such offset.
> >
> > 	For example, the function tnt4882_init() is accessing CMDR, HSSEL, AUXCR, etc.
> > 	Ref: https://sourceforge.net/p/linux-gpib/code/HEAD/tree/trunk/linux-gpib/drivers/gpib/tnt4882/tnt4882_init.c
> > <https://sourceforge.net/p/linux-gpib/code/HEAD/tree/trunk/linux-gpib/drivers/gpib/tnt4882/tnt4882_init.c>
> >
> > 	However, the physical base address for these accesses is PBAR1 without the 0x100 offset (see 'iobase' in tnt4882_init.c) ,
> > 	and then used, without any 0x100 offset, at tnt_writeb (see tnt4882.h).
> > 	Ref: https://sourceforge.net/p/linux-gpib/code/HEAD/tree/trunk/linux-gpib/drivers/gpib/tnt4882/tnt4882.h
> > <https://sourceforge.net/p/linux-gpib/code/HEAD/tree/trunk/linux-gpib/drivers/gpib/tnt4882/tnt4882.h>
> >
> > 	Do you have any hint about why this is working? Am I missing something?. I just want to understand why it works.
> >
> >
> >
> >
> >
> > The chip is controlled by the code in mite.[ch]
> > In mite.h you will see the define for CHAN_OFFSET and in mite.c see the function mite_dump_regs()
> > cheers,
> > /d
> 
> I had already noticed CHAN_OFFSET, but this offset is being applied on PBAR0 to obtain access
> to DMA status/Control registers (not to the 4882 register set), which by the way is totally wrong
> according to the manual (unless I'm missing something obvious or using a deprecated one).
> Ref: http://www.ni.com/pdf/manuals/370595b.pdf (page 3-1 or page 3-3)
> 
> Could it be that the manual is wrong and the 0x100 ofset is on PBAR0??

Just for the record.

The tnt4882 driver worked well both with and without adding an offset.
I tried to read/write registers manually with devmem and it seems that the reserved memory described in
the manual works as a mirror of the memory at offset 0x100.
# I also confirmed that the Linux GPIB driver is indeed accessing without offset, CHAN_OFFSET has nothing to do.

Thanks,
Daniel






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