MIPS: Generic: Support GIC in EIC mode

Web:        https://git.kernel.org/torvalds/c/7bf8b16d1b60419c865e423b907a05f413745b3e
Commit:     7bf8b16d1b60419c865e423b907a05f413745b3e
Parent:     0ef1559a20b939f314ea18a810fc486fc9307b77
Refname:    refs/heads/master
Author:     Matt Redfearn <[email protected]>
AuthorDate: Fri Jan 5 10:31:07 2018 +0000
Committer:  James Hogan <[email protected]>
CommitDate: Mon Feb 5 14:36:03 2018 +0000

    MIPS: Generic: Support GIC in EIC mode
    
    The GIC supports running in External Interrupt Controller (EIC) mode,
    and will signal this via cpu_has_veic if enabled in hardware. Currently
    the generic kernel will panic if cpu_has_veic is set - but the GIC can
    legitimately set this flag if either configured to boot in EIC mode, or
    if the GIC driver enables this mode. Make the kernel not panic in this
    case, and instead just check if the GIC is present. If so, use it's CPU
    local interrupt routing functions. If an EIC is present, but it is not
    the GIC, then the kernel does not know how to get the VIRQ for the CPU
    local interrupts and should panic. Support for alternative EICs being
    present is needed here for the generic kernel to support them.
    
    Suggested-by: Paul Burton <[email protected]>
    Signed-off-by: Matt Redfearn <[email protected]>
    Cc: Ralf Baechle <[email protected]>
    Cc: [email protected]
    Patchwork: https://patchwork.linux-mips.org/patch/18191/
    Signed-off-by: James Hogan <[email protected]>
---
 arch/mips/generic/irq.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c
index 394f8161e462..cb7fdaeef426 100644
--- a/arch/mips/generic/irq.c
+++ b/arch/mips/generic/irq.c
@@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
 {
 	int mips_cpu_fdc_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_fdc_irq = gic_get_c0_fdc_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else if (cp0_fdc_irq >= 0)
 		mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
 	else
@@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
 {
 	int mips_cpu_perf_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_perf_irq = gic_get_c0_perfcount_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else if (cp0_perfcount_irq >= 0)
 		mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 	else
@@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
 {
 	int mips_cpu_timer_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_timer_irq = gic_get_c0_compare_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else
 		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 
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