Re: atomic-up.h speedup : compared with irq disable/enable
Robert Wisniewski <[email protected]>
| Newsgroups | gmane.linux.kernel.tracing |
|---|---|
| Message-ID | <[email protected]> |
PowerpC certainly has atomic operations in the form of ll/sc (load linked/store conditional), that is also available on MIPS and ALPA - all RISC chips. One uses ll/sc to design atomimc ups such as atomic_inc, CAS, etc Robert Wisniewski K42 MP OS, CPO, and CSO Projects Advanced Operating Systems IBM T.J. Watson Research Center 914-945-3181 http://www.research.ibm.com/K42/ [email protected] ---- Sergei Shtylyov writes: > Hello. > > Mathieu Desnoyers wrote: > > Some more information about the non LOCKed atomic ops that I now use on SMP : > > > A test ran on a 3GHz Pentium 4 shows that (20000 loops) : > > > irq save/restore pair 210.60 ns > > > > cmpxchg 49.46 ns > > (76 % speedup) > > cmpxchg-up (no lock prefix) 9.00 ns > > (95 % speedup) > > > Does anyone still believe that cli()/sti() is faster ? :) > > Alas, it's not so for RISCs anyway -- they don't have RMW type > instructions with memory desctinations, so you still have to use cli/sti (or > locking). > I guess we also need to benchmark this on some RISCs like ARM/MIPS/PPC... > > > Mathieu > > WBR, Sergei > _______________________________________________ > Ltt-dev mailing list > [email protected] > http://listserv.shafik.org/mailman/listinfo/ltt-dev