Re: atomic-up.h speedup : compared with irq disable/enable

Hello.

Robert Wisniewski wrote:

> PowerpC certainly has atomic operations in the form of ll/sc (load

    You meant to say lwarx/stwcx? ll/sc are MIPS insns.

> linked/store conditional), that is also available on MIPS and ALPA - all
> RISC chips.

    So what? That's effectively the same ad x86 LOCK prefix, and is purely for 
SMP, and we're talking about LOCKless implementaion which speeds atomic ops 
considerably on x86 but doesn't apply to RISCs.

> One uses ll/sc to design atomimc ups such as atomic_inc, CAS, etc

    Thank you for educationg me. ;-)

WBR, Sergei