Re: atomic-up.h speedup : compared with irq disable/enable

Sergei Shtylyov writes:
 > Hello.
 > 
 > Robert Wisniewski wrote:
 > 
 > > PowerpC certainly has atomic operations in the form of ll/sc (load
 > 
 >     You meant to say lwarx/stwcx? ll/sc are MIPS insns.

yeh sorry I think of load linked/stored conditional as the general class.

 > 
 > > linked/store conditional), that is also available on MIPS and ALPA - all
 > > RISC chips.
 > 
 >     So what? That's effectively the same ad x86 LOCK prefix, and is purely for 
 > SMP, and we're talking about LOCKless implementaion which speeds atomic ops 
 > considerably on x86 but doesn't apply to RISCs.

I have to say I'm not super familiar with x86 instruction set, but after a
little investigation I understand the a LOCKless atomic op is around 25 or
so cycles, where adding the lock for SMP brings it up to 150 or so.  I
would submit that the ll/sc or lw/st is essentially equivalent.  If you
perform only on a local processor you do not need the isync (PPC) and
you'll get about 12 cycles for the lw, the ops, and then 12 cycles for the
st which comes to about 30 or roughly equivalent to the x86.  Then when you
want to use for SMP, you need an isync, which significantly increases the
time similarly to the x86 locked atomic op.

You're right though, there is a qualitative difference in that the atomic
op on the UP x86 is uninterruptable, where it would be possible even on UP
to be interrupted in the middle of an atomic operation implemented with
load linked/store conditional primitives.

 > 
 > > One uses ll/sc to design atomimc ups such as atomic_inc, CAS, etc
 > 
 >     Thank you for educationg me. ;-)

sorry, you'd be surprised though on LKML the number of people who really
don't understand such issues :-)

-bob

Robert Wisniewski
K42 MP OS, CPO, and CSO Projects
Advanced Operating Systems
IBM T.J. Watson Research Center
914-945-3181
http://www.research.ibm.com/K42/
[email protected]