Re: atomic-up.h speedup : compared with irq disable/enable

* Robert Wisniewski ([email protected]) wrote:
> You're right though, there is a qualitative difference in that the atomic
> op on the UP x86 is uninterruptable, where it would be possible even on UP
> to be interrupted in the middle of an atomic operation implemented with
> load linked/store conditional primitives.
> 

In our case, however, my understanding is that because the store conditional
primitive only succeeds if the memory area has not been modified since the load
linked, we are sure that even in the UP case, a NMI that would come right
between those two instructions would simply cause the sc to fail, thus retrying
the operation. Please correct me if I am wrong.

Mathieu


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