an ultimate question about "at least 7 insn"

Hello Grant,

Some time ago we spoke about some programming note like in pa11_acd.pdf:
[snip]
Software may rely upon this instruction translation in order to improve
performance in process dispatch. For example, in this code sequence:
    SSM 0,gr0       ; initial RSM, SSM or MTSM
    LDW             ; set up process state
    .               ; must be at least 7 instructions
    .               ; between the system mask instrs
    .
    LDW
    RSM 8,gr0       ; set PSW Q-bit to 0
    MTCTL reg1,cr20 ; set up IIASQ
[snip]

My question: is that request of 7 insn is hard-coded somewhere in silicon or
much more a logical value because of cache line size (e.g. 32 byte on a d380
and as an insn is 32 bit wide == 4 byte)? 

Why? because I noticed that recent system like n4k seems to have a bigger
cacheline (according jda patch 64 byte), though.

Tia,
    Joel---
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