Re: an ultimate question about "at least 7 insn"

On Wed, Jan 31, 2007 at 11:00:38AM +0100, Joel Soete wrote:
> Hello Grant,
> 
> Some time ago we spoke about some programming note like in pa11_acd.pdf:
> [snip]
> Software may rely upon this instruction translation in order to improve
> performance in process dispatch. For example, in this code sequence:
>     SSM 0,gr0       ; initial RSM, SSM or MTSM
>     LDW             ; set up process state
>     .               ; must be at least 7 instructions
>     .               ; between the system mask instrs
>     .
>     LDW
>     RSM 8,gr0       ; set PSW Q-bit to 0
>     MTCTL reg1,cr20 ; set up IIASQ
> [snip]
> 
> My question: is that request of 7 insn is hard-coded somewhere in silicon or
> much more a logical value because of cache line size (e.g. 32 byte on a d380
> and as an insn is 32 bit wide == 4 byte)?
> 

I believe the pipeline is 8 stages deep on pre-pa8800 processors, which
basically means we're insuring there's no dependency on the effect of
the SSM from when it is decoded to when it retires. (This could also have
been implemented completely in hardware by stalling the pipeline once
the processor decoded the SSM, no clue why it wasn't... jsm?)