latest tools for linux sh
Fabio Giovagnini <[email protected]> Fri, 3 Sep 2004 09:50:38 +0000
| Newsgroups | gmane.linux.ports.sh.devel,gmane.linux.ports.sh.general |
|---|---|
| Organization | Walbro Italy |
| Message-ID | <[email protected]> |
Hi all, I'm tring to build from scratch the toolschain for linux-sh.
I tried to follow the how available at
http://linuxsh.sourceforge.net/docs/abe/20010320-gcc2.97/README_E.php3
but using more recent version of the tools, I cannot obtain a sucessfull end
of the process.
What are the latest tested versions and how exactly they have to be
configured?
Thanks a lot
Fabio
On Friday 27 August 2004 21:45, Alex Song wrote:
> Hello,
>
> Here's the patch and 2 files for SH7705.
>
> Thanks,
>
> Alex
>
>
> ******** patch ********
>
> Index: arch/sh/Kconfig
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/Kconfig,v
> retrieving revision 1.57
> diff -u -r1.57 Kconfig
> --- arch/sh/Kconfig 15 Aug 2004 16:59:25 -0000 1.57
> +++ arch/sh/Kconfig 27 Aug 2004 21:26:29 -0000
> @@ -280,6 +280,11 @@
>
> endchoice
>
> +config SH7705_CACHE_32KB
> + bool "Enable 32KB cache size for SH7705"
> + depends on CPU_SUBTYPE_SH7705
> + default y
> +
> config MMU
> bool "Support for memory management hardware"
> depends on !CPU_SH2
>
> Index: arch/sh/boards/se/770x/irq.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/boards/se/770x/irq.c,v
> retrieving revision 1.4
> diff -u -r1.4 irq.c
> --- arch/sh/boards/se/770x/irq.c 22 Feb 2004 22:44:36 -0000 1.4
> +++ arch/sh/boards/se/770x/irq.c 27 Aug 2004 21:26:30 -0000
> @@ -12,6 +12,7 @@
> #include <linux/init.h>
> #include <linux/irq.h>
> #include <asm/irq.h>
> +#include <asm/io.h>
> #include <asm/se/se.h>
>
> /*
> @@ -30,6 +31,32 @@
> * 12: mouse
> * 14: ide0
> */
> +#if defined(CONFIG_CPU_SUBTYPE_SH7705)
> + /* Disable all interrupts */
> + ctrl_outw(0, BCR_ILCRA);
> + ctrl_outw(0, BCR_ILCRB);
> + ctrl_outw(0, BCR_ILCRC);
> + ctrl_outw(0, BCR_ILCRD);
> + ctrl_outw(0, BCR_ILCRE);
> + ctrl_outw(0, BCR_ILCRF);
> + ctrl_outw(0, BCR_ILCRG);
> + /* This is default value */
> + make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2);
> + make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa);
> + make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5);
> + make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8);
> + make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc);
> + make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe);
> + make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */
> + make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd);
> + make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9);
> + make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1);
> + make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf);
> + make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb);
> + make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7);
> + make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6);
> + make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4);
> +#else
> make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
> make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
> make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
> @@ -50,4 +77,5 @@
> /* NOTE: #2 and #13 are not used on PC */
> make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
> make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
> +#endif
> }
>
> Index: arch/sh/boards/se/770x/mach.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/boards/se/770x/mach.c,v
> retrieving revision 1.6
> diff -u -r1.6 mach.c
> --- arch/sh/boards/se/770x/mach.c 3 Aug 2003 03:05:10 -0000 1.6
> +++ arch/sh/boards/se/770x/mach.c 27 Aug 2004 21:26:30 -0000
> @@ -33,6 +33,8 @@
> .mv_nr_irqs = 32,
> #elif defined(CONFIG_CPU_SUBTYPE_SH7709)
> .mv_nr_irqs = 61,
> +#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
> + .mv_nr_irqs = 86,
> #endif
>
> .mv_inb = se_inb,
>
> Index: arch/sh/kernel/sh_ksyms.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/kernel/sh_ksyms.c,v
> retrieving revision 1.13
> diff -u -r1.13 sh_ksyms.c
> --- arch/sh/kernel/sh_ksyms.c 5 Jun 2004 17:17:34 -0000 1.13
> +++ arch/sh/kernel/sh_ksyms.c 27 Aug 2004 21:26:30 -0000
> @@ -99,7 +99,6 @@
> DECLARE_EXPORT(__movstr);
>
> #ifdef CONFIG_CPU_SH4
> -
> DECLARE_EXPORT(__movstr_i4_even);
> DECLARE_EXPORT(__movstr_i4_odd);
> DECLARE_EXPORT(__movstrSI12_i4);
> @@ -110,6 +109,14 @@
> EXPORT_SYMBOL(flush_dcache_page);
> EXPORT_SYMBOL(__flush_purge_region);
> #endif
> +
> +#if defined(CONFIG_SH7705_CACHE_32KB)
> +EXPORT_SYMBOL(flush_cache_all);
> +EXPORT_SYMBOL(flush_cache_range);
> +EXPORT_SYMBOL(flush_dcache_page);
> +EXPORT_SYMBOL(__flush_purge_region);
> +#endif
> +
> EXPORT_SYMBOL(flush_tlb_page);
> EXPORT_SYMBOL(__down_trylock);
>
> Index: arch/sh/kernel/traps.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/kernel/traps.c,v
> retrieving revision 1.18
> diff -u -r1.18 traps.c
> --- arch/sh/kernel/traps.c 12 May 2004 16:19:27 -0000 1.18
> +++ arch/sh/kernel/traps.c 27 Aug 2004 21:26:30 -0000
> @@ -438,7 +438,7 @@
> case 0x0F00: /* bf/s lab */
> ret = handle_unaligned_delayslot(regs);
> if (ret==0) {
> -#if defined(CONFIG_CPU_SH4)
> +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
> if ((regs->sr & 0x00000001) != 0)
> regs->pc += 4; /* next after slot */
> else
> @@ -451,7 +451,7 @@
> case 0x0D00: /* bt/s lab */
> ret = handle_unaligned_delayslot(regs);
> if (ret==0) {
> -#if defined(CONFIG_CPU_SH4)
> +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
> if ((regs->sr & 0x00000001) == 0)
> regs->pc += 4; /* next after slot */
> else
>
> Index: arch/sh/kernel/cpu/sh3/probe.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/kernel/cpu/sh3/probe.c,v
> retrieving revision 1.1
> diff -u -r1.1 probe.c
> --- arch/sh/kernel/cpu/sh3/probe.c 8 Jul 2004 13:52:22 -0000 1.1
> +++ arch/sh/kernel/cpu/sh3/probe.c 27 Aug 2004 21:26:30 -0000
> @@ -67,10 +67,25 @@
>
> cpu_data->flags |= CPU_HAS_MMU_PAGE_ASSOC;
> } else { /* 7709A or 7729 */
> +#if defined(CONFIG_CPU_SUBTYPE_SH7705)
> +#if defined(CONFIG_SH7705_CACHE_32KB)
> + cpu_data->dcache.way_incr = (1 << 13);
> + cpu_data->dcache.entry_mask = 0x1ff0;
> + cpu_data->dcache.sets = 512;
> + ctrl_outl(CCR_CACHE_32KB, CCR3);
> +#else
> + cpu_data->dcache.way_incr = (1 << 12);
> + cpu_data->dcache.entry_mask = 0xff0;
> + cpu_data->dcache.sets = 256;
> + ctrl_outl(CCR_CACHE_16KB, CCR3);
> +#endif
> + cpu_data->type = CPU_SH7705;
> +#else
> cpu_data->dcache.way_incr = (1 << 12);
> cpu_data->dcache.entry_mask = 0xff0;
> cpu_data->dcache.sets = 256;
> cpu_data->type = CPU_SH7729;
> +#endif
> }
>
> /*
>
> Index: arch/sh/mm/Makefile
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/mm/Makefile,v
> retrieving revision 1.10
> diff -u -r1.10 Makefile
> --- arch/sh/mm/Makefile 16 Mar 2004 22:48:05 -0000 1.10
> +++ arch/sh/mm/Makefile 27 Aug 2004 21:26:30 -0000
> @@ -19,5 +19,7 @@
> ifdef CONFIG_MMU
> obj-$(CONFIG_CPU_SH3) += tlb-sh3.o
> obj-$(CONFIG_CPU_SH4) += tlb-sh4.o ioremap.o
> +obj-$(CONFIG_SH7705_CACHE_32KB) += pg-sh7705.o
> endif
>
> +obj-$(CONFIG_SH7705_CACHE_32KB) += cache-sh7705.o
>
> Index: arch/sh/mm/tlb-sh3.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/arch/sh/mm/tlb-sh3.c,v
> retrieving revision 1.4
> diff -u -r1.4 tlb-sh3.c
> --- arch/sh/mm/tlb-sh3.c 2 May 2004 01:46:30 -0000 1.4
> +++ arch/sh/mm/tlb-sh3.c 27 Aug 2004 21:26:30 -0000
> @@ -40,6 +40,16 @@
> if (vma && current->active_mm != vma->vm_mm)
> return;
>
> +#if defined(CONFIG_SH7705_CACHE_32KB)
> + struct page *page;
> + page = pte_page(pte);
> + if (VALID_PAGE(page) && !test_bit(PG_mapped, &page->flags)) {
> + unsigned long phys = pte_val(pte) & PTE_PHYS_MASK;
> + __flush_wback_region((void *)P1SEGADDR(phys), PAGE_SIZE);
> + __set_bit(PG_mapped, &page->flags);
> + }
> +#endif
> +
> local_irq_save(flags);
>
> /* Set PTEH register */
>
> Index: drivers/mtd/maps/Kconfig
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/drivers/mtd/maps/Kconfig,v
> retrieving revision 1.9
> diff -u -r1.9 Kconfig
> --- drivers/mtd/maps/Kconfig 15 Aug 2004 16:59:28 -0000 1.9
> +++ drivers/mtd/maps/Kconfig 27 Aug 2004 21:26:30 -0000
> @@ -424,11 +424,19 @@
>
> config MTD_SOLUTIONENGINE
> tristate "CFI Flash device mapped on Hitachi SolutionEngine"
> - depends on SUPERH && MTD_CFI && MTD_REDBOOT_PARTS
> + depends on SUPERH && MTD_CFI
> help
> This enables access to the flash chips on the Hitachi SolutionEngine
> and similar boards. Say 'Y' if you are building a kernel for such a board.
>
> +config MTD_SUPERH_RESERVE
> + hex "Default reserved Flash size"
> + depends on MTD_SOLUTIONENGINE
> + default 300000
> + help
> + The reserved memory is used by kernel and ram disk themselves. It's
> + starting from 0.
> +
> config MTD_MPC1211
> tristate "CFI Flash device mapped on Interface MPC-1211"
> depends on SUPERH
>
> Index: drivers/serial/sh-sci.c
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.c,v
> retrieving revision 1.23
> diff -u -r1.23 sh-sci.c
> --- drivers/serial/sh-sci.c 4 Aug 2004 01:04:29 -0000 1.23
> +++ drivers/serial/sh-sci.c 27 Aug 2004 21:26:30 -0000
> @@ -333,7 +333,7 @@
>
> #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
> #if defined(CONFIG_CPU_SH3)
> -/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/
> +/* For SH7705, SH7707, SH7709, SH7709A, SH7729, SH7300*/
> static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
> {
> unsigned int fcr_val = 0;
> @@ -1140,6 +1140,35 @@
> .irqs = SCI_IRQS,
> .init_pins = sci_init_pins_sci,
> },
> +#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
> + {
> + .port = {
> + .membase = (void *)SCIF0,
> + .mapbase = SCIF0,
> + .iotype = SERIAL_IO_MEM,
> + .irq = 55,
> + .ops = &sci_uart_ops,
> + .flags = ASYNC_BOOT_AUTOCONF,
> + .line = 0,
> + },
> + .type = PORT_SCIF,
> + .irqs = SH3_IRDA_IRQS,
> + .init_pins = sci_init_pins_scif,
> + },
> + {
> + .port = {
> + .membase = (void *)SCIF2,
> + .mapbase = SCIF2,
> + .iotype = SERIAL_IO_MEM,
> + .irq = 59,
> + .ops = &sci_uart_ops,
> + .flags = ASYNC_BOOT_AUTOCONF,
> + .line = 1,
> + },
> + .type = PORT_SCIF,
> + .irqs = SH3_SCIF_IRQS,
> + .init_pins = sci_init_pins_scif,
> + }
> #elif defined(CONFIG_CPU_SUBTYPE_SH7707) ||
> defined(CONFIG_CPU_SUBTYPE_SH7709) {
> .port = {
> @@ -1582,7 +1611,7 @@
> /* Register the KGDB console so we get messages (d'oh!) */
> static int __init kgdb_console_init(void)
> {
> - register_console(&kgdb_console);
> + register_console(&kgdb_console);
> return 0;
> }
>
> Index: drivers/serial/sh-sci.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/drivers/serial/sh-sci.h,v
> retrieving revision 1.13
> diff -u -r1.13 sh-sci.h
> --- drivers/serial/sh-sci.h 4 Aug 2004 01:04:29 -0000 1.13
> +++ drivers/serial/sh-sci.h 27 Aug 2004 21:26:30 -0000
> @@ -58,6 +58,21 @@
> # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
> # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
> # define SCI_AND_SCIF
> +#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
> +# define SCIF0 0xA4400000
> +# define SCIF2 0xA4410000
> +# define SCSMR_Ir 0xA44A0000
> +# define IRDA_SCIF SCIF0
> +# define SCI_NPORTS 2
> +# define SCPCR 0xA4000116
> +# define SCPDR 0xA4000136
> +
> +/* Set the clock source,
> + * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
> + * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
> + */
> +# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
> +# define SCIF_ONLY
> #elif defined(CONFIG_SH_RTS7751R2D)
> # define SCI_NPORTS 1
> # define SCSPTR1 0xffe0001c /* 8 bit SCI */
> @@ -166,16 +181,16 @@
> #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
>
> /* SCxSR SCIF */
> -#define SCIF_ER 0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_TEND 0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_TDFE 0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_BRK 0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_FER 0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_PER 0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_RDF 0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> -#define SCIF_DR 0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
> +#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
>
> -#if defined(CONFIG_CPU_SUBTYPE_SH7300)
> +#if defined(CONFIG_CPU_SUBTYPE_SH7300) ||
> defined(CONFIG_CPU_SUBTYPE_SH7705) #define SCIF_ORER 0x0200
> #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK |
> SCIF_ORER) #define SCIF_RFDC_MASK 0x007f
> @@ -204,7 +219,7 @@
> # define SCxSR_ERRORS(port) SCIF_ERRORS
> # define SCxSR_RDxF(port) SCIF_RDF
> # define SCxSR_TDxE(port) SCIF_TDFE
> -#if defined(CONFIG_CPU_SUBTYPE_SH7300)
> +#if defined(CONFIG_CPU_SUBTYPE_SH7300) ||
> defined(CONFIG_CPU_SUBTYPE_SH7705) # define SCxSR_ORER(port) SCIF_ORER
> #else
> # define SCxSR_ORER(port) 0x0000
> @@ -212,12 +227,13 @@
> # define SCxSR_FER(port) SCIF_FER
> # define SCxSR_PER(port) SCIF_PER
> # define SCxSR_BRK(port) SCIF_BRK
> -#if defined(CONFIG_CPU_SUBTYPE_SH7300)
> +#if defined(CONFIG_CPU_SUBTYPE_SH7300) ||
> defined(CONFIG_CPU_SUBTYPE_SH7705) # define SCxSR_RDxF_CLEAR(port)
> (sci_in(port,SCxSR)&0xfffc) # define SCxSR_ERROR_CLEAR(port)
> (sci_in(port,SCxSR)&0xfd73) # define SCxSR_TDxE_CLEAR(port)
> (sci_in(port,SCxSR)&0xffdf) # define SCxSR_BREAK_CLEAR(port)
> (sci_in(port,SCxSR)&0xffe3) #else
> +/* SH7705 can also use this, clearing is same between 7705 and 7709 and
> 7300 */ # define SCxSR_RDxF_CLEAR(port) 0x00fc
> # define SCxSR_ERROR_CLEAR(port) 0x0073
> # define SCxSR_TDxE_CLEAR(port) 0x00df
> @@ -321,7 +337,7 @@
> }
>
> #ifdef CONFIG_CPU_SH3
> -#if defined(CONFIG_CPU_SUBTYPE_SH7300)
> +#if defined(CONFIG_CPU_SUBTYPE_SH7300) ||
> defined(CONFIG_CPU_SUBTYPE_SH7705) #define SCIF_FNS(name, scif_offset,
> scif_size) \
> CPU_SCIF_FNS(name, scif_offset, scif_size)
> #else
> @@ -347,7 +363,7 @@
> CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
> #endif
>
> -#if defined(CONFIG_CPU_SUBTYPE_SH7300)
> +#if defined(CONFIG_CPU_SUBTYPE_SH7300) ||
> defined(CONFIG_CPU_SUBTYPE_SH7705) SCIF_FNS(SCSMR, 0x00, 16)
> SCIF_FNS(SCBRR, 0x04, 8)
> SCIF_FNS(SCSCR, 0x08, 16)
> @@ -436,6 +452,15 @@
> return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
> return 1;
> }
> +#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
> +static inline int sci_rxd_in(struct uart_port *port)
> +{
> + if (port->mapbase == SCIF0)
> + return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
> + if (port->mapbase == SCIF2)
> + return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
> + return 1;
> +}
> #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
> defined(CONFIG_CPU_SUBTYPE_SH7751) || \
> defined(CONFIG_CPU_SUBTYPE_SH4_202)
> @@ -531,6 +556,8 @@
>
> #if defined(CONFIG_CPU_SUBTYPE_SH7300)
> #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
> +#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
> +#define SCBRR_VALUE(bps) (((PCLK*2)+16*bps)/(32*bps)-1)
> #elif !defined(__H8300H__) && !defined(__H8300S__)
> #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
> #else
>
> Index: include/asm-sh/bugs.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/bugs.h,v
> retrieving revision 1.6
> diff -u -r1.6 bugs.h
> --- include/asm-sh/bugs.h 4 Aug 2004 01:04:30 -0000 1.6
> +++ include/asm-sh/bugs.h 27 Aug 2004 21:26:31 -0000
> @@ -26,7 +26,7 @@
> case CPU_SH7604:
> *p++ = '2';
> break;
> - case CPU_SH7708 ... CPU_SH7300:
> + case CPU_SH7705 ... CPU_SH7300:
> *p++ = '3';
> break;
> case CPU_SH7750 ... CPU_SH4_501:
>
> Index: include/asm-sh/page.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/page.h,v
> retrieving revision 1.8
> diff -u -r1.8 page.h
> --- include/asm-sh/page.h 16 Mar 2004 22:48:05 -0000 1.8
> +++ include/asm-sh/page.h 27 Aug 2004 21:26:31 -0000
> @@ -42,7 +42,13 @@
> extern void clear_page_slow(void *to);
> extern void copy_page_slow(void *to, void *from);
>
> -#if defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) ||
> !defined(CONFIG_MMU) +#if defined(CONFIG_SH7705_CACHE_32KB) &&
> defined(CONFIG_MMU)
> +struct page;
> +extern void clear_user_page(void *to, unsigned long address, struct page
> *pg); +extern void copy_user_page(void *to, void *from, unsigned long
> address, struct page *pg); +extern void __clear_user_page(void *to, void
> *orig_to);
> +extern void __copy_user_page(void *to, void *from, void *orig_to);
> +#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) ||
> !defined(CONFIG_MMU) #define clear_user_page(page, vaddr,
> pg) clear_page(page)
> #define copy_user_page(to, from, vaddr, pg) copy_page(to, from)
> #elif defined(CONFIG_CPU_SH4)
> @@ -101,6 +107,7 @@
> #ifndef CONFIG_DISCONTIGMEM
> #define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >>
> PAGE_SHIFT)) #define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) +
> __MEMORY_START) +#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
> #endif
>
> /* PFN start number, because of __MEMORY_START */
>
> Index: include/asm-sh/pgtable.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/pgtable.h,v
> retrieving revision 1.22
> diff -u -r1.22 pgtable.h
> --- include/asm-sh/pgtable.h 16 Jun 2004 20:49:12 -0000 1.22
> +++ include/asm-sh/pgtable.h 27 Aug 2004 21:26:31 -0000
> @@ -285,7 +285,7 @@
> extern unsigned int kobjsize(const void *objp);
> #endif /* !CONFIG_MMU */
>
> -#ifdef CONFIG_CPU_SH4
> +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
> #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
> extern inline pte_t ptep_get_and_clear(pte_t *ptep);
> #endif
>
> Index: include/asm-sh/cpu-sh3/cache.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/cpu-sh3/cache.h,v
> retrieving revision 1.3
> diff -u -r1.3 cache.h
> --- include/asm-sh/cpu-sh3/cache.h 16 Jul 2003 04:08:29 -0000 1.3
> +++ include/asm-sh/cpu-sh3/cache.h 27 Aug 2004 21:26:31 -0000
> @@ -26,5 +26,12 @@
> #define CCR_CACHE_ENABLE CCR_CACHE_CE
> #define CCR_CACHE_INVALIDATE CCR_CACHE_CF
>
> +#if defined(CONFIG_CPU_SUBTYPE_SH7705)
> +#define CCR3 0xa40000b4
> +#define CCR_CACHE_16KB 0x00010000
> +#define CCR_CACHE_32KB 0x00020000
> +#endif
> +
> +
> #endif /* __ASM_CPU_SH3_CACHE_H */
>
> Index: include/asm-sh/cpu-sh3/cacheflush.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/cpu-sh3/cacheflush.h,v
> retrieving revision 1.4
> diff -u -r1.4 cacheflush.h
> --- include/asm-sh/cpu-sh3/cacheflush.h 16 Jun 2004 15:21:48 -0000 1.4
> +++ include/asm-sh/cpu-sh3/cacheflush.h 27 Aug 2004 21:26:31 -0000
> @@ -25,6 +25,46 @@
> * Caches are indexed (effectively) by physical address on SH-3, so
> * we don't need them.
> */
> +
> +#if defined(CONFIG_SH7705_CACHE_32KB)
> +
> +/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like
> the + * SH4. Unlike the SH4 this is a unified cache so we need to do some
> work + * in mmap when 'exec'ing a new binary
> + */
> + /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
> +#define CACHE_ALIAS 0x00001000
> +
> +struct page;
> +struct mm_struct;
> +struct vm_area_struct;
> +
> +extern void flush_cache_all(void);
> +extern void flush_cache_mm(struct mm_struct *mm);
> +extern void flush_cache_range(struct vm_area_struct *vma, unsigned long
> start, + unsigned long end);
> +extern void flush_cache_page(struct vm_area_struct *vma, unsigned long
> addr); +extern void flush_dcache_page(struct page *pg);
> +extern void flush_icache_range(unsigned long start, unsigned long end);
> +extern void flush_icache_page(struct vm_area_struct *vma, struct page
> *page); +
> +#define flush_dcache_mmap_lock(mapping) do { } while (0)
> +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
> +
> +/* SH3 has unified cache so no special action needed here */
> +#define flush_cache_sigtramp(vaddr) do { } while (0)
> +#define flush_page_to_ram(page) do { } while (0)
> +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
> +
> +#define p3_cache_init() do { } while (0)
> +
> +#define PG_mapped PG_arch_1
> +
> +/* We provide our own get_unmapped_area to avoid cache alias issue */
> +#define HAVE_ARCH_UNMAPPED_AREA
> +
> +#else
> +
> #define flush_cache_all() do { } while (0)
> #define flush_cache_mm(mm) do { } while (0)
> #define flush_cache_range(vma, start, end) do { } while (0)
> @@ -41,5 +81,7 @@
>
> #define HAVE_ARCH_UNMAPPED_AREA
>
> +#endif
> +
> #endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
>
> Index: include/asm-sh/se/se.h
> ===================================================================
> RCS file: /cvsroot/linuxsh/linux/include/asm-sh/se/se.h,v
> retrieving revision 1.2
> diff -u -r1.2 se.h
> --- include/asm-sh/se/se.h 1 Nov 2002 17:19:31 -0000 1.2
> +++ include/asm-sh/se/se.h 27 Aug 2004 21:26:31 -0000
> @@ -36,7 +36,11 @@
> #define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */
> #define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */
> #define PA_LED 0xb0c00000 /* LED */
> +#if defined(CONFIG_CPU_SUBTYPE_SH7705)
> +#define PA_BCR 0xb0e00000
> +#else
> #define PA_BCR 0xb1400000 /* FPGA */
> +#endif
>
> #define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */
> #define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */
> @@ -64,6 +68,10 @@
> #define BCR_ILCRF (PA_BCR + 10)
> #define BCR_ILCRG (PA_BCR + 12)
>
> +#if defined(CONFIG_CPU_SUBTYPE_SH7705)
> +#define IRQ_STNIC 12
> +#else
> #define IRQ_STNIC 10
> +#endif
>
> #endif /* __ASM_SH_HITACHI_SE_H */
>
>
> Signed-off-by: Alex Song <[email protected]>
>
>
> ********* arch/sh/mm/pg-sh7705.c **********
>
> /*
> * arch/sh/mm/pg-sh7705.c
> *
> * Copyright (C) 1999, 2000 Niibe Yutaka
> * Copyright (C) 2004 Alex Song
> *
> * This file is subject to the terms and conditions of the GNU General
> Public * License. See the file "COPYING" in the main directory of this
> archive * for more details.
> *
> */
>
> #include <linux/init.h>
> #include <linux/mman.h>
> #include <linux/mm.h>
> #include <linux/threads.h>
> #include <asm/addrspace.h>
> #include <asm/page.h>
> #include <asm/pgtable.h>
> #include <asm/processor.h>
> #include <asm/cache.h>
> #include <asm/io.h>
> #include <asm/uaccess.h>
> #include <asm/pgalloc.h>
> #include <asm/mmu_context.h>
> #include <asm/cacheflush.h>
>
>
> static inline void __flush_purge_virtual_region(void *p1, void *virt, int
> size) {
> unsigned long v;
> unsigned long begin, end;
> unsigned long p1_begin;
>
>
> begin = L1_CACHE_ALIGN((unsigned long)virt);
> end = L1_CACHE_ALIGN((unsigned long)virt + size);
>
> p1_begin = (unsigned long)p1 & ~(L1_CACHE_BYTES - 1);
> /* do this the slow way as we may not have TLB entries
> * for virt yet. */
> for (v = begin; v < end; v+=L1_CACHE_BYTES) {
> unsigned long p;
> unsigned long ways, addr;
>
> p = __pa(p1_begin);
>
> ways = cpu_data->dcache.ways;
> addr = CACHE_OC_ADDRESS_ARRAY;
>
> do {
> unsigned long data;
>
> addr |= (v & cpu_data->dcache.entry_mask);
>
> data = ctrl_inl(addr);
> if ((data & CACHE_PHYSADDR_MASK) == (p & CACHE_PHYSADDR_MASK)) {
> data &= ~(SH_CACHE_UPDATED|SH_CACHE_VALID);
> ctrl_outl(data, addr);
> }
> addr += cpu_data->dcache.way_incr;
>
> } while(--ways);
>
> p1_begin += L1_CACHE_BYTES;
> }
> }
>
> /*
> * clear_user_page
> * @to: P1 address
> * @address: U0 address to be mapped
> */
> void clear_user_page(void *to, unsigned long address, struct page *pg)
> {
> struct page *page = virt_to_page(to);
>
> __set_bit(PG_mapped, &page->flags);
> if ((( address ^ (unsigned long)to) & CACHE_ALIAS) == 0){
> clear_page(to);
> __flush_wback_region(to, PAGE_SIZE);
> }
> else {
> __flush_purge_virtual_region(to,
> (void *)(address & 0xfffff000),
> PAGE_SIZE);
> clear_page(to);
> __flush_wback_region(to, PAGE_SIZE);
> }
> }
>
> /*
> * copy_user_page
> * @to: P1 address
> * @from: P1 address
> * @address: U0 address to be mapped
> */
> void copy_user_page(void *to, void *from, unsigned long address, struct
> page *pg) {
> struct page *page = virt_to_page(to);
>
>
> __set_bit(PG_mapped, &page->flags);
> if (((address ^ (unsigned long)to) & CACHE_ALIAS) == 0) {
> copy_page(to, from);
> __flush_wback_region(to, PAGE_SIZE);
> }
> else {
> __flush_purge_virtual_region(to, (void *)(address & 0xfffff000),
> PAGE_SIZE); copy_page(to, from);
> __flush_wback_region(to, PAGE_SIZE);
> }
> }
>
> /*
> * For SH7705, we have our own implementation for ptep_get_and_clear
> * Copied from pg-sh4.c
> */
> inline pte_t ptep_get_and_clear(pte_t *ptep)
> {
> pte_t pte = *ptep;
>
> pte_clear(ptep);
> if (!pte_not_present(pte)) {
> unsigned long pfn = pte_pfn(pte);
> if (pfn_valid(pfn)) {
> struct page *page = pfn_to_page(pfn);
> struct address_space *mapping = page_mapping(page);
> if (!mapping || !mapping_writably_mapped(mapping))
> __clear_bit(PG_mapped, &page->flags);
> }
> }
> return pte;
> }
>
> Signed-off-by: Alex Song <[email protected]>
>
>
> ********* arch/sh/mm/cache-sh7705.c **********
>
> /*
> * arch/sh/mm/cache-sh7705.c
> *
> * Copyright (C) 1999, 2000 Niibe Yutaka
> * Copyright (C) 2004 Alex Song
> *
> * This file is subject to the terms and conditions of the GNU General
> Public * License. See the file "COPYING" in the main directory of this
> archive * for more details.
> *
> */
>
> #include <linux/init.h>
> #include <linux/mman.h>
> #include <linux/mm.h>
> #include <linux/threads.h>
> #include <asm/addrspace.h>
> #include <asm/page.h>
> #include <asm/pgtable.h>
> #include <asm/processor.h>
> #include <asm/cache.h>
> #include <asm/io.h>
> #include <asm/uaccess.h>
> #include <asm/pgalloc.h>
> #include <asm/mmu_context.h>
> #include <asm/cacheflush.h>
>
> /* The 32KB cache on the SH7705 suffers from the same synonym problem
> * as SH4 CPUs */
>
> #define __pte_offset(address) \
> ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
> #define pte_offset(dir, address) ((pte_t *) pmd_page_kernel(*(dir)) + \
> __pte_offset(address))
>
> static inline void cache_wback_all(void)
> {
> unsigned long ways, waysize, addrstart;
>
> ways = cpu_data->dcache.ways;
> waysize = cpu_data->dcache.sets;
> waysize <<= cpu_data->dcache.entry_shift;
>
> addrstart = CACHE_OC_ADDRESS_ARRAY;
>
> do {
> unsigned long addr;
>
> for (addr = addrstart;
> addr < addrstart + waysize;
> addr += cpu_data->dcache.linesz)
> {
> unsigned long data;
>
> data = ctrl_inl(addr);
> if ((data & (SH_CACHE_UPDATED|SH_CACHE_VALID))
> == (SH_CACHE_UPDATED|SH_CACHE_VALID))
> ctrl_outl(data & ~(SH_CACHE_VALID |SH_CACHE_UPDATED), addr);
> }
> addrstart += cpu_data->dcache.way_incr;
>
> } while (--ways);
> }
>
> /*
> * Write back the range of D-cache, and purge the I-cache.
> *
> * Called from kernel/module.c:sys_init_module and routine for a.out
> format. */
> void flush_icache_range(unsigned long start, unsigned long end)
> {
> __flush_wback_region((void *)start, end - start);
> }
>
>
> /*
> * Writeback&Invalidate the D-cache of the page
> */
> static void __flush_dcache_page(unsigned long phys)
> {
> unsigned long ways, waysize, addrstart;
> unsigned long flags;
>
> phys |= SH_CACHE_VALID;
>
> /* Here, phys is the physical address of the page. We check all the tags in
> * the cache for those with the same page number as this page (by masking
> off * the lowest 2 bits of the 19-bit tag; these bits are derived from the
> offset * within in the 4k page). Matching valid entries are invalidated. *
> * Since 2 bits of the cache index are derived from the virtual page
> number, * knowing this would reduce the number of cache entries to be
> searched by a * factor of 4. However this function exists to deal with
> potential cache * aliasing, therefore the optimisation is probably not
> possible.
> */
> local_irq_save(flags);
> jump_to_P2();
>
> ways = cpu_data->dcache.ways;
> waysize = cpu_data->dcache.sets;
> waysize <<= cpu_data->dcache.entry_shift;
>
> addrstart = CACHE_OC_ADDRESS_ARRAY;
>
> do {
> unsigned long addr;
>
> for (addr = addrstart;
> addr < addrstart + waysize;
> addr += cpu_data->dcache.linesz)
> {
> unsigned long data;
>
> data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
> if (data == phys) {
> data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
> ctrl_outl(data, addr);
> }
> }
> addrstart += cpu_data->dcache.way_incr;
>
> } while (--ways);
>
> back_to_P1();
> local_irq_restore(flags);
> }
>
>
> /*
> * Write back & invalidate the D-cache of the page.
> * (To avoid "alias" issues)
> */
> void flush_dcache_page(struct page *page)
> {
> if (test_bit(PG_mapped, &page->flags))
> __flush_dcache_page(PHYSADDR(page_address(page)));
> }
>
> void flush_cache_all(void)
> {
> unsigned long flags;
>
> local_irq_save(flags);
> jump_to_P2();
>
> cache_wback_all();
> back_to_P1();
> local_irq_restore(flags);
> }
>
> void flush_cache_mm(struct mm_struct *mm)
> {
> /* Is there any good way? */
> /* XXX: possibly call flush_cache_range for each vm area */
> flush_cache_all();
> }
>
> /*
> * Write back and invalidate D-caches.
> *
> * START, END: Virtual Address (U0 address)
> *
> * NOTE: We need to flush the _physical_ page entry.
> * Flushing the cache lines for U0 only isn't enough.
> * We need to flush for P1 too, which may contain aliases.
> */
> void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end)
> {
>
> /*
> * We could call flush_cache_page for the pages of these range,
> * but it's not efficient (scan the caches all the time...).
> *
> * We can't use A-bit magic, as there's the case we don't have
> * valid entry on TLB.
> */
> flush_cache_all();
> }
>
> /*
> * Write back and invalidate I/D-caches for the page.
> *
> * ADDRESS: Virtual Address (U0 address)
> */
> void flush_cache_page(struct vm_area_struct *vma, unsigned long address)
> {
> pgd_t *dir;
> pmd_t *pmd;
> pte_t *pte;
> pte_t entry;
> unsigned long phys;
>
> dir = pgd_offset(vma->vm_mm, address);
> pmd = pmd_offset(dir, address);
> if (pmd_none(*pmd) || pmd_bad(*pmd))
> return;
> pte = pte_offset(pmd, address);
> entry = *pte;
> if (pte_none(entry) || !pte_present(entry))
> return;
>
> phys = pte_val(entry)&PTE_PHYS_MASK;
> __flush_dcache_page(phys);
> }
>
> /*
> * This is called when a page-cache page is about to be mapped into a
> * user process' address space. It offers an opportunity for a
> * port to ensure d-cache/i-cache coherency if necessary.
> *
> * Not entirely sure why this is necessary on SH3 with 32K cache but
> * without it we get occasional "Memory fault" when loading a program.
> */
> void flush_icache_page(struct vm_area_struct *vma, struct page *page)
> {
> __flush_purge_region(page_address(page), PAGE_SIZE);
> }
>
> Signed-off-by: Alex Song <[email protected]>
>
>
>
>
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