Re: Fwd: SMI tuning
Paolo Mantegazza <[email protected]> Tue, 27 Feb 2018 14:05:26 +0100
| Newsgroups | gmane.linux.real-time.rtai |
|---|---|
| Message-ID | <[email protected]> |
This is a multi-part message in MIME format. --===============1680149029702314473== Content-Type: multipart/alternative; boundary="------------92879CD63613148C06361615" Content-Language: en-US This is a multi-part message in MIME format. --------------92879CD63613148C06361615 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable For what I know if you have SMI_LOCK enabled, then you should see if it=20 can be disabled at the BIOS level. Nonetheless, somebody told to me that there are BIOS allowing it while=20 others do not (most?). Paolo On 02/27/2018 01:30 PM, William Montgomery wrote: > Forgot to CC the list... > ---------- Forwarded message ---------- > From: *William Montgomery* > Date: Tue, Feb 27, 2018 at 7:27 AM > Subject: Re: [Rtai] SMI tuning > To: Paolo Mantegazza > > > I have used the SMISPV program and see the same results - I am unable=20 > to clear any SMI bits.=C2=A0 It appears as if the SMI control enable bi= ts=20 > are somehow locked.=C2=A0 It could also be that the UEFI firmware detec= ts=20 > that I have changed the bits and it then sets them back to the default=20 > value. > > I have looked at the related README files trying to find any clues.=C2=A0= =20 > Now I am reading the Intel datasheet for the chipset and suspect that=20 > the SMI_LOCK bit may be set. I was hoping that someone on this list=20 > may have already run into this problem. > > Regards, > Wm > > On Tue, Feb 27, 2018 at 6:53 AM, Paolo Mantegazza=20 > <[email protected] <mailto:[email protected]>> wrote: > > The interacting interface, SMISPV, might be of further help. Have > a look also at the related READMEs. > > Paolo > > > On 02/26/2018 06:33 PM, William Montgomery wrote: >> I am moving to a new hardware platform due to obsolescence issues >> and testing the latency with the kern/latency app shows some >> mostly 10-22usec ovl max but some occasional large spikes >> (2msec). In the past I have used rtai_smi module to fix this type >> problem and now I have added the new Intel SMI chipset but and >> unable to mask the SMI bits.=C2=A0 This motherboard contains: >> >> Intel(R) Xeon(R) W-2133 CPU @ 3.60GHz -- Skylake >> Intel C422 chipset >> >> When I load the rtai_smi module, I see: >> >> [ 2386.756382] RTAI: Intel SMI chipset found (8086:a2d3), >> enabling SMI workaround. >> [ 2386.756409] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, >> PERIODIC, LEGACY_USB2, INTEL_USB2. >> [ 2386.756411] Original SMI configuration value 0xffffff03 has >> been cleared with mask =3D 0x1 (saved mask setting 0x1), new value= 0 >> xffffff03. >> [ 2386.756413] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, >> PERIODIC, LEGACY_USB2, INTEL_USB2. >> >> Does anyone have experience with these new chipsets? >> >> Regards, >> Wm >> >> >> _______________________________________________ >> Rtai mailing list >> [email protected] <mailto:[email protected]> >> https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai >> <https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai> > > > > _______________________________________________ > Rtai mailing list > [email protected] <mailto:[email protected]> > https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai > <https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai> > > > > > > _______________________________________________ > Rtai mailing list > [email protected] > https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai --------------92879CD63613148C06361615 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable <html> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Dutf= -8"> </head> <body text=3D"#000000" bgcolor=3D"#FFFFFF"> <div class=3D"moz-cite-prefix">For what I know if you have SMI_LOCK enabled, then you should see if it can be disabled at the BIOS level. <br> Nonetheless, somebody told to me that there are BIOS allowing it while others do not (most?).<br> <br> Paolo<br> <br> On 02/27/2018 01:30 PM, William Montgomery wrote:<br> </div> <blockquote type=3D"cite" cite=3D"mid:[email protected]= ail.com"> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Du= tf-8"> <div dir=3D"ltr">Forgot to CC the list...<br> <div class=3D"gmail_quote">---------- Forwarded message ---------= -<br> From: <b class=3D"gmail_sendername">William Montgomery</b><br> Date: Tue, Feb 27, 2018 at 7:27 AM<br> Subject: Re: [Rtai] SMI tuning<br> To: Paolo Mantegazza<br> <br> <br> <div dir=3D"ltr">I have used the SMISPV program and see the sam= e results - I am unable to clear any SMI bits.=C2=A0 It appears= as if the SMI control enable bits are somehow locked.=C2=A0 It c= ould also be that the UEFI firmware detects that I have changed the bits and it then sets them back to the default value. <div><br> </div> <div>I have looked at the related README files trying to find any clues.=C2=A0 Now I am reading the Intel datasheet = for the chipset and suspect that the SMI_LOCK bit may be set.=C2= =A0 I was hoping that someone on this list may have already run into this problem.</div> <div><br> </div> <div>Regards,</div> <div>Wm</div> </div> <div class=3D"HOEnZb"> <div class=3D"h5"> <div class=3D"gmail_extra"><br> <div class=3D"gmail_quote">On Tue, Feb 27, 2018 at 6:53 AM, Paolo Mantegazza <span dir=3D"ltr"><<a href=3D"mailto:[email protected]" target=3D"_blank" moz-do-not-send=3D"true">paolo.ma= [email protected]</a>></span> wrote:<br> <blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> <div text=3D"#000000" bgcolor=3D"#FFFFFF"> <div class=3D"m_-4386237998365796775m_-480417798545211= 4047moz-cite-prefix">The interacting interface, SMISPV, might be of further help. Have a look also at the related READMEs.<br> <br> Paolo <div> <div class=3D"m_-4386237998365796775h5"><br> <br> On 02/26/2018 06:33 PM, William Montgomery wrote:<br> </div> </div> </div> <blockquote type=3D"cite"> <div> <div class=3D"m_-4386237998365796775h5"> <div dir=3D"ltr">I am moving to a new hardwar= e platform due to obsolescence issues and testing the latency with the kern/latency app shows some mostly 10-22usec ovl max but some occasional large spikes (2msec).=C2= =A0 In the past I have used rtai_smi module to fix this type problem and now I have added the new Intel SMI chipset but and unable to mask the SMI bits.=C2=A0 This motherboar= d contains: <div><br> </div> <div>Intel(R) Xeon(R) W-2133 CPU @ 3.60GHz -- Skylake<br> </div> <div>Intel C422 chipset</div> <div><br> </div> <div>When I load the rtai_smi module, I see:</div> <div><br> </div> <div> <div>[ 2386.756382] RTAI: Intel SMI chipset found (8086:a2d3), enabling SMI workaround.</div> <div>[ 2386.756409] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, PERIODIC, LEGACY_USB2, INTEL_USB2.</div= > <div>[ 2386.756411] Original SMI configuration value 0xffffff03 has been cleared with mask =3D 0x1 (saved mask setting 0x1), new value 0</div> <div>xffffff03.</div> <div>[ 2386.756413] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, PERIODIC, LEGACY_USB2, INTEL_USB2.</div= > </div> <div><br> </div> <div>Does anyone have experience with these new chipsets?</div> <div><br> </div> <div>Regards,</div> <div>Wm</div> </div> <br> <fieldset class=3D"m_-4386237998365796775m_-480417798= 5452114047mimeAttachmentHeader"></fieldset> <br> </div> </div> <pre>______________________________<wbr>_________= ________ Rtai mailing list <a class=3D"m_-4386237998365796775m_-4804177985452114047moz-txt-link-abbr= eviated" href=3D"mailto:[email protected]" target=3D"_blank" moz-do-not-send=3D= "true">[email protected]</a> <a class=3D"m_-4386237998365796775m_-4804177985452114047moz-txt-link-free= text" href=3D"https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai" target= =3D"_blank" moz-do-not-send=3D"true">https://mail.rtai.org/cgi-bin/<wbr>m= ailman/listinfo/rtai</a></pre> </blockquote> <p><br> </p> </div> <br> ______________________________<wbr>_________________<= br> Rtai mailing list<br> <a href=3D"mailto:[email protected]" target=3D"_blank" moz-do-not-send=3D"true">[email protected]</a><br> <a href=3D"https://mail.rtai.org/cgi-bin/mailman/listi= nfo/rtai" rel=3D"noreferrer" target=3D"_blank" moz-do-not-send=3D"true">https://mail.rtai.org/cgi-= bin/<wbr>mailman/listinfo/rtai</a><br> </blockquote> </div> <br> </div> </div> </div> </div> <br> </div> <br> <fieldset class=3D"mimeAttachmentHeader"></fieldset> <br> <pre wrap=3D"">_______________________________________________ Rtai mailing list <a class=3D"moz-txt-link-abbreviated" href=3D"mailto:[email protected]">Rtai@= rtai.org</a> <a class=3D"moz-txt-link-freetext" href=3D"https://mail.rtai.org/cgi-bin/= mailman/listinfo/rtai">https://mail.rtai.org/cgi-bin/mailman/listinfo/rta= i</a></pre> </blockquote> <p><br> </p> </body> </html> --------------92879CD63613148C06361615-- --===============1680149029702314473== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Rtai mailing list [email protected] https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai --===============1680149029702314473==--