Fwd: SMI tuning

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Forgot to CC the list...
---------- Forwarded message ----------
From: William Montgomery
Date: Tue, Feb 27, 2018 at 7:27 AM
Subject: Re: [Rtai] SMI tuning
To: Paolo Mantegazza


I have used the SMISPV program and see the same results - I am unable to
clear any SMI bits.  It appears as if the SMI control enable bits are
somehow locked.  It could also be that the UEFI firmware detects that I
have changed the bits and it then sets them back to the default value.

I have looked at the related README files trying to find any clues.  Now I
am reading the Intel datasheet for the chipset and suspect that the
SMI_LOCK bit may be set.  I was hoping that someone on this list may have
already run into this problem.

Regards,
Wm

On Tue, Feb 27, 2018 at 6:53 AM, Paolo Mantegazza <
[email protected]> wrote:

> The interacting interface, SMISPV, might be of further help. Have a look
> also at the related READMEs.
>
> Paolo
>
>
> On 02/26/2018 06:33 PM, William Montgomery wrote:
>
> I am moving to a new hardware platform due to obsolescence issues and
> testing the latency with the kern/latency app shows some mostly 10-22usec
> ovl max but some occasional large spikes (2msec).  In the past I have used
> rtai_smi module to fix this type problem and now I have added the new Intel
> SMI chipset but and unable to mask the SMI bits.  This motherboard
> contains:
>
> Intel(R) Xeon(R) W-2133 CPU @ 3.60GHz -- Skylake
> Intel C422 chipset
>
> When I load the rtai_smi module, I see:
>
> [ 2386.756382] RTAI: Intel SMI chipset found (8086:a2d3), enabling SMI
> workaround.
> [ 2386.756409] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, PERIODIC,
> LEGACY_USB2, INTEL_USB2.
> [ 2386.756411] Original SMI configuration value 0xffffff03 has been
> cleared with mask = 0x1 (saved mask setting 0x1), new value 0
> xffffff03.
> [ 2386.756413] Bits enabled: GBL_SMI, EOS (special), MCSMI, TCO, PERIODIC,
> LEGACY_USB2, INTEL_USB2.
>
> Does anyone have experience with these new chipsets?
>
> Regards,
> Wm
>
>
> _______________________________________________
> Rtai mailing [email protected]://mail.rtai.org/cgi-bin/mailman/listinfo/rtai
>
>
>
> _______________________________________________
> Rtai mailing list
> [email protected]
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<div dir=3D"ltr">Forgot to CC the list...<br><div class=3D"gmail_quote">---=
------- Forwarded message ----------<br>From: <b class=3D"gmail_sendername"=
>William Montgomery</b><br>Date: Tue, Feb 27, 2018 at 7:27 AM<br>Subject: R=
e: [Rtai] SMI tuning<br>To: Paolo Mantegazza<br><br><br><div dir=3D"ltr">I =
have used the SMISPV program and see the same results - I am unable to clea=
r any SMI bits.=C2=A0 It appears as if the SMI control enable bits are some=
how locked.=C2=A0 It could also be that the UEFI firmware detects that I ha=
ve changed the bits and it then sets them back to the default value.<div><b=
r></div><div>I have looked at the related README files trying to find any c=
lues.=C2=A0 Now I am reading the Intel datasheet for the chipset and suspec=
t that the SMI_LOCK bit may be set.=C2=A0 I was hoping that someone on this=
 list may have already run into this problem.</div><div><br></div><div>Rega=
rds,</div><div>Wm</div></div><div class=3D"HOEnZb"><div class=3D"h5"><div c=
lass=3D"gmail_extra"><br><div class=3D"gmail_quote">On Tue, Feb 27, 2018 at=
 6:53 AM, Paolo Mantegazza <span dir=3D"ltr">&lt;<a href=3D"mailto:paolo.ma=
[email protected]" target=3D"_blank">[email protected]</a>&gt;</s=
pan> wrote:<br><blockquote class=3D"gmail_quote" style=3D"margin:0 0 0 .8ex=
;border-left:1px #ccc solid;padding-left:1ex">
 =20
   =20
 =20
  <div text=3D"#000000" bgcolor=3D"#FFFFFF">
    <div class=3D"m_-4386237998365796775m_-4804177985452114047moz-cite-pref=
ix">The interacting interface, SMISPV,
      might be of further help. Have a look also at the related READMEs.<br=
>
      <br>
      Paolo<div><div class=3D"m_-4386237998365796775h5"><br>
      <br>
      On 02/26/2018 06:33 PM, William Montgomery wrote:<br>
    </div></div></div>
    <blockquote type=3D"cite"><div><div class=3D"m_-4386237998365796775h5">
     =20
      <div dir=3D"ltr">I am moving to a new hardware platform due to
        obsolescence issues and testing the latency with the
        kern/latency app shows some mostly 10-22usec ovl max but some
        occasional large spikes (2msec).=C2=A0 In the past I have used
        rtai_smi module to fix this type problem and now I have added
        the new Intel SMI chipset but and unable to mask the SMI bits.=C2=
=A0
        This motherboard contains:
        <div><br>
        </div>
        <div>Intel(R) Xeon(R) W-2133 CPU @ 3.60GHz -- Skylake<br>
        </div>
        <div>Intel C422 chipset</div>
        <div><br>
        </div>
        <div>When I load the rtai_smi module, I see:</div>
        <div><br>
        </div>
        <div>
          <div>[ 2386.756382] RTAI: Intel SMI chipset found (8086:a2d3),
            enabling SMI workaround.</div>
          <div>[ 2386.756409] Bits enabled: GBL_SMI, EOS (special),
            MCSMI, TCO, PERIODIC, LEGACY_USB2, INTEL_USB2.</div>
          <div>[ 2386.756411] Original SMI configuration value
            0xffffff03 has been cleared with mask =3D 0x1 (saved mask
            setting 0x1), new value 0</div>
          <div>xffffff03.</div>
          <div>[ 2386.756413] Bits enabled: GBL_SMI, EOS (special),
            MCSMI, TCO, PERIODIC, LEGACY_USB2, INTEL_USB2.</div>
        </div>
        <div><br>
        </div>
        <div>Does anyone have experience with these new chipsets?</div>
        <div><br>
        </div>
        <div>Regards,</div>
        <div>Wm</div>
      </div>
      <br>
      <fieldset class=3D"m_-4386237998365796775m_-4804177985452114047mimeAt=
tachmentHeader"></fieldset>
      <br>
      </div></div><pre>______________________________<wbr>_________________
Rtai mailing list
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iated" href=3D"mailto:[email protected]" target=3D"_blank">[email protected]</a>
<a class=3D"m_-4386237998365796775m_-4804177985452114047moz-txt-link-freete=
xt" href=3D"https://mail.rtai.org/cgi-bin/mailman/listinfo/rtai" target=3D"=
_blank">https://mail.rtai.org/cgi-bin/<wbr>mailman/listinfo/rtai</a></pre>
    </blockquote>
    <p><br>
    </p>
  </div>

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