Re: Home Grown ActionTec Development Daughterboard

Scott Christensen,

> I made a post a while back about using FPGA / CPLD on the daughtercard, 
> as was on the Gameboy thingy:
> 
> http://www.express.org/pipermail/actionhack/2004-February/000702.html
> 
> The Gameboy unit used the FPGA as a controller to external SDRAM & 
> flash, as well as to provide up to 64 bits of external GPIO.  Check out 
> the links in the above post; lots of good info there as they used the 
> FPGA to do many of the things I see possible with this Actiontec modem.
> 
> For FPGA / CPLDs, here are freeware modules to program into them:
> 
> http://www.opencores.com/browse.cgi/by_category
> 
> Of note are the following free cores:
> 
> General-Purpose I/O (GPIO) Core
> UART 16550 core
> USB 2.0 Function Core  (I assume this is a master controller)
> 
> The challenge I see is doing anything practical with only 8 data lines 
> and 4 address lines to work with via J5, but as you point out there 
> could be an intelligent controller programmed into the FPGA that is 
> essentially a "bus expander" device requiring funky device driver.

OK...I took a look at OpenCores and now I "get it".  Pretty cool stuff!!

I spent 10 years doing HDL design in Verilog making "bleeding-edge" 
full-custom chips, so I know the possibilities are endless with this kind 
of thing.  I did not realize how cheap these FPGA's have gotten or more 
importantly, there seem to be usable HDL design tools that are free!

I say leave the existing (cheap) UART/USB recovery logic in place so that 
the Actiontec always can boot with a console present, and then add a 
little more area to the existing PCB to support the Xilinx chip, and then 
add something like a compact flash slot (or two).

As for J5's 8-bit port: The Actiontec's console UART takes 8 of the 16 
addressable locations.  That leaves 8 locations for expansion.  To support 
16-bit I/O with full 32-bit addressing, make the remaining 8 ports I/O map 
something like this...

  0x8: register for address bits 0-7 (R/W)
  0x9: register for address bits 8-15 (R/W)
  0xa: register for address bits 16-23 (R/W)
  0xb: register for address bits 24-31 (R/W)
  0xc: data register bits 0-7 (R/W)
  0xd: data register bits 8-15 (R/W)
  0xe: control/config/status register (R/W)
  0xf: read/write data at current address

The "mode" for data read/write (e.g., 8-bit or 16-bit) and the behavior of 
the 32-bit address register (e.g., auto increment or not) would be defined 
by bits in the control/config/status register.

Maybe we let the read/write to register 0xf return/send data bits 0-7. 
(Maybe we eliminate register 0xc.)  For 16-bit I/O mode, register 0xd 
latches and/or holds the high data byte.  (This is like the AVR 
microcontroller's work for 16-bit timer registers access.)

Anyway, this can be made to work without too much extra programming overhead.

> BTW, I got a reply from Digilent that their $15 CPLD 40 pin dip module 
> is 4 weeks from production.  But since we have surface mount experts on 
> the list, maybe we don't need it and could directly use the CoolRunner 
> II - XC2C256 CPLD. :-)

Surface mount is your friend! :-)

I wanna' do this...

Best regards,

Bruce

-- 
  Bruce D. Lightner
  Lightner Engineering
  La Jolla, California
  Voice: +1-858-551-4011
  FAX: +1-858-551-0777
  Email: lightner-2huV/[email protected]
  URL: http://www.lightner.net/lightner/bruce

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