Re: Challenge: CCL port to the RPi Pico (RP2040)

Ron Garret <[email protected]> Sun, 28 Jul 2024 11:10:19 -0700
Newsgroups gmane.lisp.openmcl.devel
Message-ID <[email protected]>
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> On Jul 28, 2024, at 10:43 AM, Carl Shapiro <[email protected]> =
wrote:
>=20
> On Sun, Jul 28, 2024 at 7:54=E2=80=AFAM Tim McNerney <[email protected] =
<mailto:[email protected]>> wrote:
> CCL already has 32-bit ARM support. There is no OS interfacing work to =
do here (only work to make up for the lack of OS).=20
>=20
> The Cortex-M processors execute Thumb-1 or Thumb-2 instructions which =
are different from 32-bit ARM instructions.  The Cortex-A designs and =
older designs from ARM with a "T" in their name support both the 32-bit =
ARM and Thumb instructions.
>=20
> On a Cortex-A and other processors that support both ISAs, code can =
switch between ISA states with the BX or BLX instruction setting the =
lower bit of the destination to 1 or 0 to specify either the Thumb or =
ARM ISA.  If someone wants to add a backend to the Cortex-M, starting =
with a working ARM backend and switching the code generator to using =
Thumb would seem like a possible way to start.

Doesn't seem like it would be very hard.  They are the same ISA, just =
different encodings.

=
https://stackoverflow.com/questions/28669905/what-is-the-difference-betwee=
n-the-arm-thumb-and-thumb-2-instruction-encodings

rg


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<html><head><meta http-equiv=3D"Content-Type" content=3D"text/html; =
charset=3Dutf-8"></head><body style=3D"word-wrap: break-word; =
-webkit-nbsp-mode: space; line-break: after-white-space;" class=3D""><br =
class=3D""><div><br class=3D""><blockquote type=3D"cite" class=3D""><div =
class=3D"">On Jul 28, 2024, at 10:43 AM, Carl Shapiro &lt;<a =
href=3D"mailto:[email protected]" =
class=3D"">[email protected]</a>&gt; wrote:</div><br =
class=3D"Apple-interchange-newline"><div class=3D""><div dir=3D"ltr" =
class=3D""><div class=3D"gmail_quote"><div dir=3D"ltr" =
class=3D"gmail_attr">On Sun, Jul 28, 2024 at 7:54=E2=80=AFAM Tim =
McNerney &lt;<a href=3D"mailto:[email protected]" target=3D"_blank" =
class=3D"">[email protected]</a>&gt; wrote:<br class=3D""></div><blockquote=
 class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-left:1px =
solid rgb(204,204,204);padding-left:1ex"><div dir=3D"auto" class=3D""><div=
 dir=3D"ltr" class=3D""><div dir=3D"ltr" class=3D""><div class=3D""><div =
class=3D"">CCL already has 32-bit ARM support. There is no OS =
interfacing work to do here (only work to make up for the <i =
class=3D"">lack</i> of =
OS).&nbsp;</div></div></div></div></div></blockquote><div class=3D""><br =
class=3D""></div><div class=3D"">The Cortex-M processors execute Thumb-1 =
or Thumb-2 instructions which are different from 32-bit ARM =
instructions.&nbsp; The Cortex-A designs and older designs from ARM with =
a "T" in their name support both the 32-bit ARM and Thumb =
instructions.</div><div class=3D""><br class=3D""></div><div class=3D"">On=
 a Cortex-A and other processors that support both ISAs, code can switch =
between ISA states with the BX or BLX instruction setting the lower bit =
of the destination to 1 or 0 to specify either the Thumb or ARM =
ISA.&nbsp; If someone wants to add a backend to the Cortex-M, starting =
with a working ARM backend and switching the code generator to using =
Thumb would seem like a possible way to =
start.</div></div></div></div></blockquote><div><br =
class=3D""></div><div>Doesn't seem like it would be very hard. =
&nbsp;They are the same ISA, just different encodings.</div><div><br =
class=3D""></div><div><a =
href=3D"https://stackoverflow.com/questions/28669905/what-is-the-differenc=
e-between-the-arm-thumb-and-thumb-2-instruction-encodings" =
class=3D"">https://stackoverflow.com/questions/28669905/what-is-the-differ=
ence-between-the-arm-thumb-and-thumb-2-instruction-encodings</a></div><div=
><br class=3D""></div></div>rg<div class=3D""><br =
class=3D""></div></body></html>=

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