Access to Lanai SRAM using DMA over the PCI bus

Vangelis Koukis <[email protected]> Wed, 16 May 2007 19:13:34 +0300
Newsgroups gmane.network.myrinet.general
Organization Computing Systems Laboratory, NTUA
Message-ID <[email protected]>
Hello all,

for a research project, I'm trying to read and write directly from/to the
SRAM of my M3F-PCIXD-2 cards, accessing it through the PCI memory-mapped
address space.

When programming another device on the same PCI segment to do DMA
writes to the physical address range where the SRAM of the Lanai
is mapped, I can get very satisfactory throughputs, in the range of
~320MB/s. It seems I'm only limited by the PCI bus itself (64bit/66MHz,
gm_debug reports 318MB/s bus_read, 378MB/s bus_write).

However, when programming the same device to do *reads* from this address
space using DMA, i.e. to fetch data from SRAM, it can't do more than
~20MB/s... When dealing with main memory, the device reads and writes
at ~300MB/s (using PC133 SDRAM).

I'm using a Supermicro P3TDE6 motherboard (Serverworks ServerSet III
HC-SL chipset, Broadcom CIOB20 PCI bridge).

Any pointers, comments, help would be greatly appreciated.

-- 
Vangelis Koukis, PhD candidate
Computing Systems Laboratory,
National Technical University of Athens.
Institute of Communication and Computer Systems (ICCS)
[email protected]