Re: Feedback on Control architecture

still waiting for a feed back about it .. Thanks ..
Best regards,
Mohamed A.Salem

On Sun, 2004-03-14 at 15:36, Mohamed Salem wrote:
> Good document Ravi, My understanding and queries are below (correct any
> wrong inference please)
> 
> **TxController and RXcontroller are hardware modules that controls the
> data-path components and its corresponding multiplexers in the TX and RX
> respectively.
> Each module would be designed as a sequencer or data-flow manager among
> the data-path elements.
> For instance: in TX, The TXcontroller will decide when to initialize
> and/or enable the CRC16 component to start processing on the pay-load
> (plain user-data) coming from the TX buffer; then it informs that CRC16
> at the end of the user-data by asserting the "Drain" signal HIGH , and
> also maintain it for 16 cycles which are needed to append the CRC16
> value from the LFSR to the pay-load.
> and so on for each module according to each processing scheme.
> 
> **The micro-controller will have a firm-ware (c-code) which should be
> simple (due to moving much of the control actions to the HW
> controllers),and the Ucontroller should be like a manager of the HW
> controllers actions. (I need an example for this scenario from your
> side) to point out for instance how the Ucontroller manage the actions
> of forinstance the TXcontroller along the processing among the data-path
> components.
> 
> ** Timerblock module: I need to know the function of it. Is it only
> sending interrupts to the Ucontroller.? and what are these interrupts. ?
> this is vague for me.
> 
> **Headerbuffer:
> This buffer stores the header of the data to be transmitted as I
> understand. (the header on which the CRC8 HEC has to be evaluated)isn't
> it ?
> I need to know why it is interacting with Ucontroller.?
> ** CS register
> IS it the current status register. In other words a register that holds
> the BT system states .. If yes , please list what states that we would
> be working with. 
> It is reasonable that CS_Reg informs the Ucontroller of the Current
> state and then the Ucontroller has a scenario to be executed represeted
> in control actions for the data-path controllers and etc.. 
> 
> Radio-Interface block: 
> 
> what does it inform the Ucontroller with and what is it getting in
> return from its side. And is this dependant on the RF that we will
> use.(we need to be independent somehow to work with all RFs available).
> 
> An explanation of the involved interactions of the control architecture
> would be very helpful for all of us...
>  
> I am looking forward to having your feedback and comments.
> 
> Ps: We are all learning here and this is the main objective; Hence Could
> u please all contribute with your understanding, feedback,
> queries...etc..The most of joy happens when many of us working as one
> hand to reach the same goal.......Think of it seriously all here and Let
> Us realize NOUR chip.we are ahead of starting off a real development
> phase of a very state-of-the-art project ...Waiting for YOU ALL>
> 
> Best Regards,
> 	Mohamed A.Salem
>  
> 
> 
> On Thu, 2004-03-11 at 03:33, Ravi Ranjan Kumar wrote:
> > Hi,
> > Yesterday i worked on a small document, which describes the way
> > i am thinking about the h/w architecture of NOUR. Please find
> > the document attached with the mail in pdf format.
> >   Comments please!!
> > Thanks and Regards
> > -- Ravi Ranjan Kumar
> > 
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