Re: FEC (Forward Error Correction)

Hi Mohamed,
Please find my answers embedded in the mail marked as Ravi>>.
-- Ravi 



---- On 28 Apr 2004 10:41:21, Mohamed Salem
([email protected]) wrote:

> Dear NOUR team, 
> 
> Regarding completion of bitstream HW specs, FEC 1/3 and FEC
2/3 details
> have to be figured out.
> 
> *FEC 1/3 for Header: 
> Input bit should be repeated three times. 0 => 000 ; 1 => 111
and so on.
> Data input in serial fashion and also output.
> Suggest an implementation and clarify the input data rate and
output
> data rate.

Ravi>> It is very clear from the application of this block it
self that each bit will be repeatede thrice. So the the input
data rate will be 1/3M Bits/s clock at the clock of 1 Mhz.

  All previous components on 1 MHZ system clock , so The
> output from FEC 1/3 will be then at 3 times faster rate or not
? 

Ravi>> By making the input bitstream 3 times slower we achieve
the rate of 1Mega Bits / second at the output fo the FEC1/3
block.

> Refer to the signal description in bitstream document
> http://www.handasarabia.org/document.php?id=110
> for previous components to know global signals for all
components
> including FEC.
> 
> *FEC 2/3 For payload: 
> 
> 2 bits at input correspond to 3 bits at output. In our scheme
every set
> of 10 bits is "injected" into the architecture shown in spec
document
> and then we Append 5 parity bits to them.
> In the implementation of the block how can we inform the
component that
> after each 10 bits append 5 bits in 5 clock cycles ; and also
how  can 
> incoming bits not being lost while appending the parity 5
bits;in the
> time of 5 cycles needed to append parity ; input data doesn't
stop. 

Ravi >> The rate of incoming bits can be controlled as it is not
a stream of data but it will be output of a tx_buffer. For each
bit that has to be read from the buffer there will be a read
strobe issued. Now in case of 2/3 FEC, there will be read_strobe
asserted for 10 clocks continuously and then it will be
deasserted for another 5 clocks after that, this will continue
till the end of the packet.

> 
> Suggest an Implementation from a controlling point of view as
the HW
> architecture is default for FEC 2/3 according to BT standard. 
> 
> It will be worth discussing also how the Parity(redundant
added bits in
> each FEC coding type) bits (check bits) are used to detect
errors and
> correct it in both types of FEC used for Header and Payload.
> 
> Note: Once, this is clarified the bit-stream HW specs will be
ready and
> complete then HDL coding phase should be taking place in
advance. 
> 
> LET US LEARN and Progress NOUR.
> 
> Thanks 
> 
> Best Regards,
> 
> 	Mohamed A.Salem 
> 
> 
> 
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> 
> Message number 136
> 
> 
> 


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Message number 137