Re: Memory Controller

Hello All,

The core for SRAM controller in the openrisc soc is meant for SRAM
memory bank that is there on XESS board.

We will b porting the design on the Altera SOPC board which has Micron
SSRAM MT8L256L32DT

If any 1 of u can plz give me links for the datasheet (have searched at
micron website...).

Regards,
-Soban
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Mohamed Salem wrote:
> 
> Hi all ,
>         This message is addressing starting a technical aggressive plan to get
> the Memory controller part of OFOQ working asap.
> 
> PLease , Have a look right now on the block diagram of the system in
> page 5 of the specs.
> 
>         The objective is to :
> 
> Integrate the memory controller IP core of (opencores) with the
> SRAM/FLASH from one side, and to the Wish-bone Interface from the other
> side (as shown in the diagram).
>         Then the wish-bone is interfacing with the openRisc CPU ..
> We need to choose a SRAM/FLASG model to be used in testing.
>         We need to be at first to be as simple as possible until we verify the
> concept then we can start complicating the components.
>         We need also to test the whole flow and communication between all
> involved components with a test bench for this purpose.
> 
> {{OpenRISC <==> Wish-Bone <<==>> Memory controller <<===>>SRAM/FLASH..}}
> 
> We need to study the features of the memory controller and how to
> connect it to the other system parts. The cores are available, what we
> need is to think how to STITCH them and then with a test bench check the
> flow of data and communication between those system parts.
> 
> Interested peers in this part should push the flow ..
> 
> Guys , I'll drive a very tight plan for OFOQ in the next few months.
> Active interested guys who were  waiting, please show up .. We wanna
> come out with it as soon as possible .. Many folks around are waiting
> for a REAL working prototype for OFOQ PDA..
> 
> Best Regards,
> 
>         Mohamed A. Salem...
> 
> --
> Mohamed A Salem
> Handasa Arabia Organization
> www.handasarabia.org
> 
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