OFOQ Memory issues

Salam all, (Salam =3D Peace =3D Greeting in Arabic language)

Thanks Mohamed for the SDRAM summary. I hope that someone from the list can
do a bridge between SDRAM and wishbone bus may be we can put it in our todo
list.
According to OFOQ-1 to do list, we have to operate the SRAM at the first
stage.
We have the following issues that we haveto consider as high priority

- May be a small summary as Mohamad did but for the SRAM on the Altera
board.
- Create wishbone to SRAM bridge (VHDL or Verilog)
- Get an estimation about the needed SRAM. We have to know if the available
SRAM is enough for our applications. UClinux and small apps. This is a
Software issue.
- Design a core that enables software to be downloaded directly to the SRAM
from teh PC. I am working on this now and I hope to get it ready soon. if you
have any suggestion let me know.


I hope to complete these issues as soon as possible

Regards,
Jamil

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Message number 85