Re: OFOQ Memory issues

Dear ALl,
Note : This reply was sent by Thursday but there was an error from the
web-mail . sorry for being blocked through an web-mail error ...
================================
OK.. Here we go .... 
This is a reply for Jamil's last message ... 

>I hope that someone from the list
> can do a bridge between SDRAM and wishbone bus may be we can put it in our
> todo list.

---- I have a query here: cann't the memory-controller interface
*directly* with the SDRAM without going through a wish-bone bus?

I think , there would be a wish-bone interface to the memory controller
from the "OR1K" CPU side only. OR1k is wish-bone compliant, hence what I do
understand so far is that we will need a wish-bone interface with the
"cores" that would communicate directly  with the "OR1k" CPU. referring to the system
block diagram in OFOQ specs - the Wish-Bone bus is from the CPU side only.
Please explain (in brief) the following topics :

- Wish-Bone SOC interface standard .
what is it about , what is it used for and how it fits in our OFOQ
context. ( in brief )
- in which parts of OFOQ would we need a Wish-bone interface
This would be of great help to all of us while progressing with the
project .. ..
-- 
> According to OFOQ-1 to do list, we have to operate the SRAM at the first
> stage

from the board specs I got that ;
SRAM banks on the board are to be used as cache memory for the implemented
processor on the FPGA -APEX device.(in our case OR1k processor)
A cool link that I would share with members is
http://www.kingston.com/tools/bits/bit3.asp
good link for simple definition of (cache) memory

Jamil, would we use it in other function  than a "cache" - is it going to be our main memory?
and On which memory would we download/port the UClinux.
We have 4 types of memory on the board :
1- main memory SDRAM
2- Flash memory.
3- SRAM (cache)
4- EEPROM .
I think we have to assign the functions of them in the context of OFOQ requirements.


Thanks in advance ....

hey Guys , please do share us in such technical discussions ! it would be
so helpful. We are all learning and we are progressing ..

Best Regards,

Mohamed A.Salem
Handasa Arabia Organization
www.handasarabia.org






On Thu, 2003-09-04 at 14:46, Jamil Khatib wrote:
> Salam all, (Salam = Peace = Greeting in Arabic language)
> 
> Thanks Mohamed for the SDRAM summary. I hope that someone from the list can
> do a bridge between SDRAM and wishbone bus may be we can put it in our todo
> list.
> According to OFOQ-1 to do list, we have to operate the SRAM at the first
> stage.
> We have the following issues that we haveto consider as high priority
> 
> - May be a small summary as Mohamad did but for the SRAM on the Altera
> board.
> - Create wishbone to SRAM bridge (VHDL or Verilog)
> - Get an estimation about the needed SRAM. We have to know if the available
> SRAM is enough for our applications. UClinux and small apps. This is a
> Software issue.
> - Design a core that enables software to be downloaded directly to the SRAM
> from teh PC. I am working on this now and I hope to get it ready soon. if you
> have any suggestion let me know.
> 
> 
> I hope to complete these issues as soon as possible
> 
> Regards,
> Jamil
> 
> -------------------------------
> OFOQ Mailing List
> Handasa Arabia Organization
> http://www.handasarabia.org
> [email protected] 
> 
> Message number 85
-- 
Mohamed A.Salem
Handasa Arabia Organization
www.handasarabia.org


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Message number 87