Re: OFOQ Memory issues

On  0, Jamil Khatib <[email protected]> wrote:
-- snip
> as far as I know that SDRAM needs to be programmed in order to operate so I
> do not think that wishbone to SDRAM is enough to operate it, the CPU must be
> active to program some internal registers in the SDRAM.
> 
Yes, as far as I know this is true, the SDRAM has some initialization to be 
done before it can be used.

> Now for thedebug port. I have not studied the debug port of the opencores
> design but I do not think we need it now we have just to download the
> software to the sram and let the CPU start from there.
> What I am planing to do is to download the software from the PC to SRAM via
> paralel port. During download the parallel port will set the CPU in reset
> mode and after download completion the CPU should start up and take the
> control over the SRAM and the parallel port will be disconnected internalley
> on the FPGA.
> What do you think about this???
> 
This is very much like the systems that I've used before.  It sounds very 
reasonable. 
                                                    Mike

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Message number 92