Re: OFOQ Memory issues

Hi everyone.

Just some observations on memory issues.

First off I Am Not An SDRAM Guru.

The EEprom on sdrams only need 5v to operate no higher voltages are require,
they talk on a simple i2c type setup.  They store details of the module.
They are very slow to talk to (Khz not Mhz) are at least 256 bytes (128
reserved for module detalis, size, type, speed, serial number, manufacturer
etc).

SDRAM does need configuration, this is for setting operation modes, the
wishbone memory controller at opencores does this for you and allows setting
all initial modes and how long to wait for module to be ready.

On module size, the ras and cas sizes are not symetrical, ie there are
usually more row than columns.

Having said all that, I am a newbie not all that experienced in
vhdl/verilog, mostly way out of date on technology, but I do have a lot of
years playing with digital stuff.


I am interested in ofoq as it is similar to something I wish to build.

	cya,	Andrew...

...Any coments I make are mine not those of my employer...

This e-mail and any attachment is for authorised use by the intended recipient(s) only. It may contain proprietary material, confidential information and/or be subject to legal privilege. It should not be copied, disclosed to, retained or used by, any other party. If you are not an intended recipient then please promptly delete this e-mail and any attachment and all copies and inform the sender. Thank you.

LogicaCMG global sponsors, Gartner Symposium, Cannes, 4th -7th November 2003

http://symposium.gartner.com/story.php.id.3323.s.5.html

Please note that LogicaCMG does not have control over content from,or availability of, this website

-------------------------------
OFOQ Mailing List
Handasa Arabia Organization
http://www.handasarabia.org
[email protected] 

Message number 96