Cores design, Spec documentation, Integrated test plan

Mohamed Salem <[email protected]> Wed, 17 Sep 2003 14:23:58 +0300
Newsgroups gmane.org.handasarabia.ofoq
Message-ID <[email protected]>
The last thread of mails concludes some tasks as  :
--Wishbone/Parallel Port Interface core --- Jamil 
--Wishbone/SSRAM interface core --- Soban ..
I think the discussion has clarified some dim issues. We have to think
of a test bench that would verify the functionality of all cores in one
context as Jamil mentioned :SRAM <-->WISHBONE<--> PP
Also we have to document a specification for each core to be designed.
If u jamil and Soban have in your mind the high level abstraction of the
designs ideas and the documentation sections " from WB / PP specs/SRAM
that might help in documenting the designs please let me know .. I can
construct the specs documents while u r working on the designs .. Also
let us discuss the test scheme in which we could validate the
integration of cores with the CPU and SSRAMs

Thanks ..
Best Regards,
Mohamed A.Salem


On Wed, 2003-09-17 at 07:23, soban shoeb chawre wrote:
> On Tue, 16 Sep 2003 Jamil Khatib wrote :
> >
> >Yes that is correct.
> >Do you plan to do teh code?
> 
> Yes.
> >
> >Regards,
> >Jamil
> >On 9/16/2003, "soban shoeb chawre" <[email protected]> 
> >wrote:
> >
> > >
> > >Ok...got it, you r going to load the SRAM
> > > from parellel port using WB burst write
> > >or (many single write) cycles, while holding the
> > >processor in reset.
> > >
> > >Thanx for prompt reply.
> > >
> > >
> > >
> > >Jamil Khatib wrote:
> > >>
> > >>Soban,
> > >>I mean that we need to convert wishbone transactions 
> >(read,write
> > >>and so) to
> > >>SRAM transactions.
> > >>SRAM  <--> WISHBONE
> > >>so that whenever I write a byte to wishbone it is written to 
> >the
> > >>SRAM and
> > >>when I read one from the wishbone it is read actually from 
> >the
> > >>SRAM.
> > >>
> > >>The block has no relation with the boot strapper. I am 
> >working
> > >>now on core
> > >>that writes to from the parallel port to WISHBONE bus so 
> >when
> > >>everything is
> > >>done we can connect both cores to write to the SRAM from the 
> >PC
> > >>
> > >>PP <--> WISHBONE
> > >>
> > >>final core should look like
> > >>
> > >>SRAM <-->WISHBONE<--> PP
> > >>
> > >>hope this helps
> > >>Regards,
> > >>Jamil
> > >>
> > >>On 9/16/2003, "soban shoeb chawre" 
> ><[email protected]>
> > >>wrote:
> > >>
> > >> ><Salam,
> > >> ><Is there anyone interested in coding the wishbone to SRAM
> > >> >bridge?
> > >> >
> > >> ><Regards,
> > >> ><Jamil
> > >> >
> > >> >WS,
> > >> >
> > >> >First of all sorry for all those mails.
> > >> >
> > >> >...actually my composer got stuck when i was sending mails
> > >> >
> > >> >I am interested in doing that..
> > >> >
> > >> >Jameel, i'd like know by "bridge" do u mean  boot strapper 
> >(i
> > >>mean
> > >> >ckt
> > >> >to load SSRAM from parellel port while keeping everything
> > >>reset)
> > >> >and controller?
> > >> >
> > >> >...or only bootstrapper?
> > >> >
> > >> >or is it that you have already made bloock diagram for 
> >boot
> > >> >strapper on which you were already working, and are 
> >looking
> > >>for
> > >> >some1 to code ?
> > >> >
> > >> >
> > >> >plz let me know
> > >> >
> > >> >
> > >> >Soban.
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
> > >> >
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-- 
Mohamed A.Salem
Handasa Arabia Organization
www.handasarabia.org


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