Re: ECC support

Hi,

> On 16 Sep 2015, at 11:48, Igor Mozolevsky <[email protected]> wrote:
> 
> On 16 September 2015 at 08:51, Bob Bishop <[email protected]> wrote:
> 
> <snip>
> 
>> - You might think that as memory density increases (ie bit cell size
> shrinks), error rates would increase. Apparently this wasn’t so up to 2009
> at least, see:
>> 
>> http://www.cs.toronto.edu/~bianca/papers/sigmetrics09.pdf
> 
> subsection 5.1:
> 
> "… Figure 6 indicates a trend towards worse error behavior
> for increased capacities, although this trend is not consis-
> tent. [etc]

That’s talking about DIMM capacity, not the capacity (density) of individual chips on which they say (at the end of the same subsection):

"The best we can conclude therefore is that any chip size effect is unlikely to dominate error rates given that the trends are not consistent across various other confounders such as age and manufacturer.”

I’ll admit to talking that point up a bit but it is counterintuitive. Memory designers have always been scared of cosmic rays etc but the suspected effects simply have not been noticeable. Most likely as they shrink features ever smaller, other factors like material purity dominate.

> There are also other environmental factors which would be more apparent in
> "lone-server" configuration vs well maintained and insulated data centres
> with very good power conditioning ;-)

Indeed, and that’s a whole other PITA. We went to colo and never looked back, but low-power options for small servers are getting better.

> -- 
> Igor M.
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--
Bob Bishop
[email protected]




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