DT overlay syntax question

Vincent DEFERT <[email protected]> Sun, 20 Jul 2025 11:03:34 +0000
Newsgroups gmane.os.netbsd.ports.arm
Message-ID <[email protected]>
Hi,

I'm trying to create overlays for optional functionalities on my ODROID C2.
It works well for I2C and UART, but not for PWM, I get a syntax error 
when defining clocks.

The overlay source is:

/dts-v1/;
/plugin/;

/ {
     /*
      * Enable PWM A.
      * Uses GPIOX.BIT6 on GPIO connector pin 33.
      */
     pwm_ab {
         status = "okay";
         pinctrl-0 = <&pwm_a_x_pins>;
         pinctrl-names = "default";
         clocks = <&xtal>, <&clkc CLKID_VID_PLL>, <&clkc 
CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV3>;
         clock-names = "xtal", "vid_pll", "fclk_div4", "fclk_div3";
     };
};

I compiled it with: dtc -@ -I dts -O dtb -o meson-gxbb-pwm_a.dtbo 
meson-gxbb-pwm_a.dts
and got a syntax error at <&clkc CLKID_VID_PLL>

I supposed it was because CLKID_VID_PLL is not defined, so I modified it 
as follows:

/dts-v1/;
/plugin/;

#include <dt-bindings/clock/gxbb-clkc.h>

/ {
     /*
      * Enable PWM A.
      * Uses GPIOX.BIT6 on GPIO connector pin 33.
      */
     pwm_ab {
         status = "okay";
         pinctrl-0 = <&pwm_a_x_pins>;
         pinctrl-names = "default";
         clocks = <&xtal>, <&clkc CLKID_VID_PLL>, <&clkc 
CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV3>;
         clock-names = "xtal", "vid_pll", "fclk_div4", "fclk_div3";
     };
};

and compiled it with: dtc -i 
/home/wrk/netbsd/src/sys/external/gpl2/dts/dist/include -@ -I dts -O dtb 
-o meson-gxbb-pwm_a.dtbo meson-gxbb-pwm_a.dts
and this time, I got a syntax error on #include!

Using the old syntax (dtc < v1.5) such as the example below gives 
exactly the same results:

/dts-v1/;
/plugin/;

/ {
     /*
      * Enable PWM A.
      * Uses GPIOX.BIT6 on GPIO connector pin 33.
      */
     fragment@0 {
         target = <&pwm_ab>;
         __overlay__ {
             status = "okay";
             pinctrl-0 = <&pwm_a_x_pins>;
             pinctrl-names = "default";
             clocks = <&xtal>, <&clkc CLKID_VID_PLL>, <&clkc 
CLKID_FCLK_DIV4>, <&clkc CLKID_FCLK_DIV3>;
             clock-names = "xtal", "vid_pll", "fclk_div4", "fclk_div3";
         };
     };
};

Do you have any suggestions as to what I can try to make it work?

Thanks