Re: MIPS Alchemy machine don't boot

Hi! Simon,


From: Simon Burge <[email protected]>
Date: Sat, 09 Jan 2010 22:49:48 +1100

> I've found the problem.  In lock_stubs.S we have the following
> code:
> 
>         .set    mips3
> 	...
>          move t1, a2
> 
> which will always generate a 64-bit move, since the ".set mips3"
> will override any -mabi=<abi> command line flag.
> 
> The following snippet from mipsX_subr.S shows what is needed.  Perhaps
> we can wrap this up in a macro?
> 
> 	/*
> 	 * Set ISA level for the assembler.
> 	 */
> 	#if defined(MIPS3)
> 		.set    mips3
> 	#endif
> 
> 	#if defined(MIPS32)
> 		.set    mips32
> 	#endif
> 
> 	#if defined(MIPS64)
> 		.set    mips64
> 	#endif

Thanks for your advice.  ;-)
My OpenMicroServer AL400(OMSAL400) boots with attached patch.  However
happen new problem on cobalt's userland.
The binary of default evbmips works big-endian.  But OMSAL400 works
little-endian...  I will build userland of evbmips-el at tonight. ;-)

Also this change needs.  I cast bsh to u_long.


Index: alchemy/au_himem_space.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/alchemy/au_himem_space.c,v
retrieving revision 1.10
diff -u -r1.10 au_himem_space.c
--- alchemy/au_himem_space.c    16 Dec 2009 08:26:14 -0000      1.10
+++ alchemy/au_himem_space.c    10 Jan 2010 05:30:07 -0000
@@ -294,7 +294,7 @@

        if (acct) {
                bus_addr_t              addr;
-               addr = ((pa - c->c_physoff) + (bsh % PAGE_SIZE));
+               addr = ((pa - c->c_physoff) + ((u_long)bsh % PAGE_SIZE));
                extent_free(c->c_extent, addr, size, EX_NOWAIT);
        }
 }


Thanks,
--
kiyohara

Index: mips/lock_stubs.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/lock_stubs.S,v
retrieving revision 1.10
diff -u -r1.10 lock_stubs.S
--- mips/lock_stubs.S	14 Dec 2009 00:46:06 -0000	1.10
+++ mips/lock_stubs.S	10 Jan 2010 05:30:09 -0000
@@ -53,7 +53,21 @@
 
 #if MIPS_HAS_LLSC != 0
 
+/*
+ * Set ISA level for the assembler.
+ */
+#if defined(MIPS3)
 	.set	mips3
+#endif
+
+#if defined(MIPS32)
+	.set	mips32
+#endif
+
+#if defined(MIPS64)
+	.set	mips64
+#endif
+
 	.set	noreorder
 	.set	noat