Re: MIPS 20Kc cache

the first thing occured to me is that the d-cache, is
physically indexd & physically tagged. i-caches are no
different. there is no change is cache opcodes.
however for the flush mechanism software must provide
the virtual address & MMU translates it to the
physical.
now it's my turn to get whacked. malta board with
bonito64 does not work (i am not talking about CPU
detection). the ethernet device seems to have
synchronization or cache handling issues. latter seems
true. 'cause the cache routines are for virtually
indexed caches. enlighten me...
 
--- [email protected] wrote:
> At Mon, 19 Aug 2002 11:36:09 +0000 (UTC), "Toru
> Nishimura" wrote:
> > MIPS 20Kc defines the cache architecture radically
> differently from
> > standard R4000 derivatives.
> 
> Eh?  In what way?  MIPS32/MIPS64 cache ops, etc.,
> are pretty much the
> same as 4k/5k.  (no VCE, though, yay. 8-)
> 
> i've not looked at the actual 20Kc docs, so whack me
> if they do
> something Weird.  8-)
> 
> 
> chris
> 


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