Re: MIPS 20Kc cache

[email protected] 19 Aug 2002 09:23:05 -0700

Newsgroups	gmane.os.netbsd.ports.mips
Message-ID	<[email protected]>

At Mon, 19 Aug 2002 11:36:09 +0000 (UTC), "Toru Nishimura" wrote:
> MIPS 20Kc defines the cache architecture radically differently from
> standard R4000 derivatives.

Eh?  In what way?  MIPS32/MIPS64 cache ops, etc., are pretty much the
same as 4k/5k.  (no VCE, though, yay. 8-)

i've not looked at the actual 20Kc docs, so whack me if they do
something Weird.  8-)

chris