re: Pausing/resuming CPU's in DDB

On Fri, 24 Feb 2012, matthew green wrote:

> FWIW, to debug some sparc smp issues i was seeing i added an NMI IPI
> that made the remote cpus log their %pc, if they weren't answering
> normal IPIs.  i never tried porting this code to sparc64 in any sense
> (and it isn't commited to sparc port anyway) because level 15 is no
> longer "NMI", as i recall anyway.
> 
> but the feature is simple to implement and use, if it works.

I don't think there's any way to generate a "NMI" IPI on V9 machines.  
Everything (including IPIs) comes in as an interrupt_vector and then is 
given a priority in software.  

Hm... Maybe what's going on is that the SMP code is turning off the 
interrupt enable bit in the pstate register rather than just increasing 
the IPL in the level register...  that would prevent any interrupts from 
being recieved and queued for later dispatch.

Eduardo