Proposal for a general purpose control subsytem.

I recently submitted this to one of my professors proposing a project to 
develop a hardware subsystem for control.
The idea is to implement the Orocos system, but instead of relying on an RTOS, 
offload the processing to a specific hardware coprocessor.
The processor would be a soft core that could then be easily extended to meet 
the needs of specific systems, only the orocos driver would need to be 
implemented as the low level SPI type drivers would be handled directly by 
the coprocessor.

My abstract is pasted below.
I thought I'd throw this out there and see what reaction I get.
Comments? Suggestions? Reasons why I'm insane?

NZG.

ABSTRACT

A Soft Core for Reconfigurable Control
Nathan Z. Gustavson (EMAC.Inc & Southern Illinois University Carbondale)
As embedded applications become more complex, traditional monolithic control
loop programs are being superceded by scheduled tasks, run as a process by an
OS. [4]This is problematic for control, because the microprocessor must also 
run
its normal tasks, (scheduling, memory management, networking, IO ports, 
etc...).
This results in a slower control loop, and a more complex project.
With the advent of the modern FPGAs, a new approach has opened, that of
using a soft core to offload some of the control work into specific, 
reconfigurable
hardware sections. [2] These soft cores can be used as building blocks to 
rapidly
build board specific embedded architectures. These fine tuned architectures 
are
ideal for control implementations since they are highly adaptable [1], and 
offer
higher throughput rates than can be achieved with software alone.
Modern microprocessors incorporate features that are not needed to implement
a control interface, such as advanced branch instructions and prediction, 
flash
memory, and external busses.[5] This project will investigate how these 
features
can be streamlined, or completely removed, to yield a single circular 
pipelined
advanced ALU which can be dedicated specifically to the task of control. This 
will
create a system that is faster, cheaper, less complex, and less power hungry
than most high end control hardware.
A soft core will be designed consisting of:
1. A small register based memory to hold a limited number of instructions.
2. An arithmatic instruction pipeline, which will handle add, subtract, 
multiply, and
divide instructions, matrix based if time and resources permit.
3. Appropriate hazard detection and avoidance logic.
4. A “rerun” unit. Motion control loops execute the same series of arithmatic
instructions over and over again on different inputs and state feedbacks. Once
the original order of execution is established, it can be remembered and
maintained until the instruction buffer is reloaded with a different 
algorithm.
5. A sensor input bus from which state data is obtained. In a complete system
this would be integrated with another soft core IO unit to pull in sensor data 
in a
pipeline parallel to the instruction pipeline.
6. A control output bus, which in a complete system would transfer the control
data to a soft core IO unit doing output.
The core will be implemented in mixed VHDL, AHDL, and schematic capture,
using Quartus II FPGA design software from Altera. Several RISC cores will be
analyzed and one (or more) chosen to strip down and modify. [6] [7].

[1] R. A. Gonçalves*, P.A. Moraes*, J. M. P. Cardoso+, D. F. WolfY, M. M.
Fernandes,R. A. F. Romero*, E. Marques* (2003)
ARCHITECT-R: A System for Reconfigurable Robots Design
Symposium on Applied Computing archive
Proceedings of the 2003 ACM symposium on Applied computing
[2] Nurprasetyo, Eko Fajar; Inoue, Akihiko; Tomiyama, Hiroyuki; Yasuura, 
Hiroto
(1998)
Soft-core processor architecture for embedded system design
IEICE Transactions on Electronics. Vol. E81-C, no. 9, pp. 1416-1423.
[3] Henrik B. Christophersen*, Wayne J. Pickell*, Adrian A. Koller†, Suresh K.
Kannan†, and Eric N. Johnson‡
Small Adaptive Flight Control Systems for
UAVs using FPGA/DSP Technology
Georgia Institute of Technology, Atlanta GA 30332-0150
[4] The real-time motion control core of the Orocos project
Bruyninckx, H. Soetens, P. Koninckx, B.
Dept. of Mech. Eng., Katholieke Univ., Leuven, Heverlee, Belgium
[5] Orocos: - http://www.orocos.org
[6]Open Cores: - http://www.opencores.org
[7]Altera soft-cores - 
http://www.altera.com/products/ip/processors/ipm-index.jsp
[8] John Paul Shen, Mikko H. Lipasti (2005)
Modern Processor Design
Fundamentals of Superscalar Processors
McGraw Hill
[9] Gene F. Franklin, J. David Powell, Abbas Emami-Naenini(2002)
Feedback Control of Dynamic Systems
Prentice Hall