Re: [PATCH 2/5] irqchip/gic-v5: Clear per-CPU IRS data on teardown

On Mon, 2026-08-10 at 13:36 +0200, Lorenzo Pieralisi wrote:
> On Mon, Aug 10, 2026 at 10:28:07AM +0000, Sascha Bischoff wrote:
> > IRS affinity setup publishes an IRS pointer and IAFFID state in the
> > per-CPU data before the remaining IRS initialization can fail. The
> > error path then frees the IRS data without clearing that published
> > state, leaving CPUs associated with freed memory.
> > 
> > On initialization failure and normal IRS teardown, clear the per-
> > CPU
> > IRS association by removing the stale pointer to irs_data. Also
> > clear
> > the per-CPU IAFFID state for any CPUs that were tied to the IRS
> > before
> > it was freed.
> > 
> > Fixes: 5cb1b6dab2de ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
> > Fixes: 35866efa52fe ("irqchip/gic-v5: Add ACPI IRS probing")
> > Link:
> > https://sashiko.dev/#/patchset/[email protected]?part=2
> > Signed-off-by: Sascha Bischoff <[email protected]>
> > ---
> >  drivers/irqchip/irq-gic-v5-irs.c | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> 
> Thank you Sascha, a minor comment below otherwise:
> 
> Reviewed-by: Lorenzo Pieralisi <[email protected]>

Thanks!

> 
> > diff --git a/drivers/irqchip/irq-gic-v5-irs.c
> > b/drivers/irqchip/irq-gic-v5-irs.c
> > index f3fce0b1e25d9..67940ea9e39b7 100644
> > --- a/drivers/irqchip/irq-gic-v5-irs.c
> > +++ b/drivers/irqchip/irq-gic-v5-irs.c
> > @@ -651,6 +651,19 @@ static int __init
> > gicv5_irs_of_init_affinity(struct device_node *node,
> >  	return ret;
> >  }
> >  
> > +static void __init gicv5_irs_clear_affinity(struct
> > gicv5_irs_chip_data *irs_data)
> > +{
> > +	int cpu;
> > +
> > +	for_each_possible_cpu(cpu) {
> > +		if (per_cpu(per_cpu_irs_data, cpu) == irs_data) {
> > +			per_cpu(cpu_iaffid, cpu).iaffid = 0;
> 
> As long we set valid to false this is not necessarily needed, 0 is a
> valid
> value.

Thanks, Lorenzo. That's a good point. I've dropped the setting of
iaffid to 0 as marking it as invalid should be sufficient.

Sascha

> 
> Thanks,
> Lorenzo
> 
> > +			per_cpu(cpu_iaffid, cpu).valid = false;
> > +			per_cpu(per_cpu_irs_data, cpu) = NULL;
> > +		}
> > +	}
> > +}
> > +
> >  static void irs_setup_pri_bits(u32 idr1)
> >  {
> >  	switch (FIELD_GET(GICV5_IRS_IDR1_PRIORITY_BITS, idr1)) {
> > @@ -773,6 +786,7 @@ static int __init gicv5_irs_of_init(struct
> > device_node *node)
> >  	return ret;
> >  
> >  out_iomem:
> > +	gicv5_irs_clear_affinity(irs_data);
> >  	iounmap(irs_base);
> >  out_err:
> >  	kfree(irs_data);
> > @@ -787,6 +801,7 @@ void __init gicv5_irs_remove(void)
> >  	gicv5_deinit_lpis();
> >  
> >  	list_for_each_entry_safe(irs_data, tmp_data, &irs_nodes,
> > entry) {
> > +		gicv5_irs_clear_affinity(irs_data);
> >  		iounmap(irs_data->irs_base);
> >  		list_del(&irs_data->entry);
> >  		kfree(irs_data);
> > @@ -951,6 +966,7 @@ static int __init gic_acpi_parse_madt_irs(union
> > acpi_subtable_headers *header,
> >  	return 0;
> >  
> >  out_map:
> > +	gicv5_irs_clear_affinity(irs_data);
> >  	iounmap(irs_base);
> >  out_release:
> >  	release_mem_region(r->start, resource_size(r));
> > -- 
> > 2.34.1