[PATCH v2 0/4] KVM: arm64: GICv5 KVM IRS review fixes

Hi all,

v1 [1] combined irqchip and KVM fixes identified by Sashiko [2] while
reviewing the GICv5 KVM IRS series [3]. Following feedback, v2 splits
the fixes into separate irqchip and KVM postings. This posting
contains the KVM fixes; the irqchip fixes are posted separately.

Changes since v1:

* Split the combined series into irqchip and KVM postings.

* Extend the out-of-range GICv5 PPI fix to reject unsupported PPIs at
  the type-validation boundary as well as in the lookup path.

* Add a fix to validate a GICv5 timer PPI before claiming its IRQ.

The fixes are:

* Free gic_kvm_info when vGIC initialisation fails because the
  maintenance interrupt is not provided but is required.

* Fix speculative accesses in the common vGIC SPI lookup which could
  previously underflow. The SPI index is now made relative to the SPI
  array before array_index_nospec() constrains it rather than
  afterwards.

* Reject GICv5 PPIs outside KVM's supported private IRQ range. These
  were previously classified as PPIs and clamped to zero, aliasing
  private IRQ 0.

* Validate the architecturally fixed GICv5 timer PPI before claiming it
  with the vGIC.

These changes are based on v7.2-rc7.

Thanks,
Sascha

[1] https://lore.kernel.org/all/[email protected]/
[2] https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff%40arm.com
[3] https://lore.kernel.org/all/[email protected]/

Sascha Bischoff (4):
  KVM: arm64: vgic: Free gic_kvm_info on initialization failure
  KVM: arm64: vgic: Prevent speculative SPI array underflow
  KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs
  KVM: arm64: Validate GICv5 timer PPIs before claiming ownership

 arch/arm64/kvm/arch_timer.c     | 5 +++--
 arch/arm64/kvm/vgic/vgic-init.c | 4 +++-
 arch/arm64/kvm/vgic/vgic.c      | 7 +++++--
 include/kvm/arm_vgic.h          | 2 ++
 4 files changed, 13 insertions(+), 5 deletions(-)

-- 
2.34.1