Re: chipsec integrity check

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The fact that this is an AMD system will cause issues with the chipsec resu=
lts.  To properly run chipsec on a system you need to have a valid configur=
ation file for the platform.  Even when using the -i flag a number of assum=
ptions are made about the register layout of the platform.  To correctly su=
pport an AMD system a number of modifications would need to be made to chip=
sec as well as a configuration would need to be provided for that specific =
platform.  Because of these issues most hardware register accesses will be =
wrong.  You will need to ignore the MMIO register dumps and base addresses.

With that said some information is still valid but may still need some addi=
tional filtering.

UEFI Variable Data:
-TrEEPhysicalPresence - TPM2 related
-SMBIOSLOG000 - Looks like a SMBIOS event was logged.
-SctCsmMemoryMapVariable - This looks to be related to legacy OS support (C=
ompatibility Support Module) and the memory map that was used to boot a leg=
acy OS.  This is normally needed for S4 resume to keep the map consistent.
-ErrOutDev - Console redirection similar to stderr used by the UEFI Shell o=
r UEFI boot loader.

PCI Dump:
Changes in these devices may be due to status registers or different device=
 states.  You would have to have information about the device to handle com=
mand and status registers as these change during runtime.  All of these cha=
nges are outside the first 0x40 bytes so they will be device specific.

I hope this helps some.

Thanks,
-Erik

From: Healer64 [mailto:Healer64(a)protonmail.com]
Sent: Friday, December 1, 2017 11:33 AM
To: Bjorge, Erik C <[email protected]>
Cc: chipsec(a)lists.01.org
Subject: RE: [chipsec] chipsec integrity check

Of course.  I did my own analysis which may save you some effort.

Of the efi variables which had changed from the baseline, very few addition=
al changes were seen after a reboot into my normal OS then a reboot into th=
e chipsec usb.  Only the ErrOutDev and SctCsmMemoryMapVariable changed and =
SctCsmMemoryMapVariable is a new variable not part of the baseline.

Here is a list of other changes that occurred with just the reboots mention=
ed above:
ec dump =3D changed
iommu config GFXVTD =3D BAR value changed, flags changed back to baseline
iommu config VTD =3D BAR value changed, some flags changed back to baseline=
 but not all
iommu status GFXVTD =3D returned to baseline
iommu status VTD =3D changed
mmio dump DMIBAR =3D changed
mmio dump GFXVTBAR =3D returned to baseline except mmio register range
mmio dump GMADR =3D changed
mmio dump GTTMADR =3D changed
mmio dump HDABAR =3D changed
mmio dump HDBAR =3D no change
mmio dump MCHBAR =3D changed
mmio dump PXPEPBAR =3D changed
mmio dump VTBAR =3D changed
mmio list =3D changed
pci dump =3D changed

Also when doing the iommu dump config GFXVTD I do get errors from chipsec. =
I couldn't capture them.  They don't show up in the log and even redirectin=
g standard out and standard error doesn't catch them, but I was able to cop=
y one from the screen.
ioremap error for 0xde0c1000-0xdec2000, requested 0x10, got 0x0

Also it occured to me I should mention this is an AMD system and chipsec co=
mplains about an unsupported platform.  Most of the functions appear to wor=
k just fine even so, but it is possible it could have some affect on the re=
sults.




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-------- Original Message --------
Subject: RE: [chipsec] chipsec integrity check
Local Time: December 1, 2017 12:27 AM
UTC Time: December 1, 2017 12:27 AM
From: erik.c.bjorge(a)intel.com<mailto:[email protected]>
To: Healer64 <Healer64(a)protonmail.com<mailto:[email protected]>>
chipsec(a)lists.01.org<mailto:[email protected]> <chipsec(a)lists.01.o=
rg<mailto:[email protected]>>


Thanks for sending the new logs.  Give us a day or so to look them over and=
 see if we can find anything new.

Thanks,
-Erik

From: chipsec [mailto:chipsec-bounces(a)lists.01.org] On Behalf Of Healer64
Sent: Thursday, November 30, 2017 4:23 PM
To: Bjorge, Erik C <erik.c.bjorge(a)intel.com<mailto:erik.c.bjorge@intel.=
com>>
Cc: chipsec(a)lists.01.org<mailto:[email protected]>
Subject: Re: [chipsec] chipsec integrity check

After a reboot, I ran the tests again.  New log is here:
https://pastebin.com/XCHrYYJF
https://pastebin.com/NiYcnxGG

Just for kicks I did a diff of the 2 instances.

https://pastebin.com/KLea3gVf



Some of the BAR values have changed again.  No longer 0.  That seems odd.

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--===============1768051367067937493==--