Re: chipsec integrity check

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Thanks, Erik that helps a great deal. I feel I understand much better what =
is happening in the hardware. I do still wonder about some of the flags tha=
t changed in the iommu vtd and gfx vtd. For example
 [04] RWBF             =3D 0 << Required Write-Buffer Flushing

Which changed from 1 to 0 and back to 1 again. Would something like that in=
dicate a configuration change or a misread?
https://pastebin.com/KLea3gVf

I did use the chipsec whitelist function using the known good bios from the=
 manufacturer and no changes to embedded executables were flagged, but just=
 as a test I ran it again using a different version of the bios firmware th=
an what is currently in use. Again no changes were found. I thought that wa=
s interesting. Maybe that version of the firmware didn't include an changes=
 to embedded executables?

> -------- Original Message --------
> Subject: RE: [chipsec] chipsec integrity check
> Local Time: December 11, 2017 1:11 PM
> UTC Time: December 11, 2017 7:11 PM
> From: erik.c.bjorge(a)intel.com
> To: Healer64 <[email protected]>
> chipsec(a)lists.01.org <[email protected]>
>
> The fact that this is an AMD system will cause issues with the chipsec re=
sults.  To properly run chipsec on a system you need to have a valid config=
uration file for the platform.  Even when using the -i flag a number of ass=
umptions are made about the register layout of the platform.  To correctly =
support an AMD system a number of modifications would need to be made to ch=
ipsec as well as a configuration would need to be provided for that specifi=
c platform.  Because of these issues most hardware register accesses will b=
e wrong.  You will need to ignore the MMIO register dumps and base addresse=
s.
>
> With that said some information is still valid but may still need some ad=
ditional filtering.
>
> UEFI Variable Data

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--===============2589897566792351318==--