Re: chipsec integrity check

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The IOMMU values may be wrong because we are looking at the wrong locations=
 in MMIO space or other platform dependencies.  If you can send us the verb=
ose log file (include the -v parameter) we should be able to see all of the=
 register reads.  This will allow us to determine if it is a platform regis=
ter layout.

The whitelist failure may be expected if you are having issues reading the =
SPI image on your platform.  I would not expect that no changes would be fo=
und though.  I would expect failures when reading the SPI image or verifyin=
g the whitelist.

Thanks,
-Erik

From: Healer64 [mailto:Healer64(a)protonmail.com]
Sent: Friday, December 15, 2017 8:32 AM
To: Bjorge, Erik C <[email protected]>
Cc: chipsec(a)lists.01.org
Subject: RE: [chipsec] chipsec integrity check


Thanks, Erik that helps a great deal. I feel I understand much better what =
is happening in the hardware. I do still wonder about some of the flags tha=
t changed in the iommu vtd and gfx vtd. For example
 [04] RWBF             =3D 0 << Required Write-Buffer Flushing

Which changed from 1 to 0 and back to 1 again. Would something like that in=
dicate a configuration change or a misread?
https://pastebin.com/KLea3gVf


I did use the chipsec whitelist function using the known good bios from the=
 manufacturer and no changes to embedded executables were flagged, but just=
 as a test I ran it again using a different version of the bios firmware th=
an what is currently in use. Again no changes were found. I thought that wa=
s interesting. Maybe that version of the firmware didn't include an changes=
 to embedded executables?

-------- Original Message --------
Subject: RE: [chipsec] chipsec integrity check
Local Time: December 11, 2017 1:11 PM
UTC Time: December 11, 2017 7:11 PM
From: erik.c.bjorge(a)intel.com<mailto:[email protected]>
To: Healer64 <Healer64(a)protonmail.com<mailto:[email protected]>>
chipsec(a)lists.01.org<mailto:[email protected]> <chipsec(a)lists.01.o=
rg<mailto:[email protected]>>


The fact that this is an AMD system will cause issues with the chipsec resu=
lts.  To properly run chipsec on a system you need to have a valid configur=
ation file for the platform.  Even when using the -i flag a number of assum=
ptions are made about the register layout of the platform.  To correctly su=
pport an AMD system a number of modifications would need to be made to chip=
sec as well as a configuration would need to be provided for that specific =
platform.  Because of these issues most hardware register accesses will be =
wrong.  You will need to ignore the MMIO register dumps and base addresses.

With that said some information is still valid but may still need some addi=
tional filtering.

UEFI Variable Data


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