Re: [OPAE] UDP parser

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Hi Volkan,

	Seems like your questions are more related to PAC card RTL design issue ra=
ther than OPAE. But here are some inputs for your reference.

1. Yes, the PAC design kit has examples to instantiate the MAC IPs (includi=
ng PHY). So you can directly handle the packets on top of MAC. Recommend to=
 use AVST interface provided by the MAC IP. Take v1.2 Acceleration Stack SD=
K for example, the design you can leverage is under /hw/samples/eth_e2e_e40=
/ inside the a10_gx_pac_ias_1_2_pv.tar.

2. The PHY & MAC is already in SDK, also the local memory interface. For DD=
R interface, it was encapsulated as AVMM interface. Example design is under=
 /hw/samples/hello_mem_afu/.  BTW, this memory interface is for local (on b=
oard) DDR access, OPAE stack has no ownership or management to that.

3. No TCP examples provided in SDK. There are commercial TOE (TCP offload e=
ngine) design or maybe some open cores. =


BRs,
Roger Chien =


-----Original Message-----

Date: Thu, 27 Dec 2018 15:19:07 +0000
From: Ali Volkan Atli <Volkan.Atli(a)argela.com.tr>
To: "opae(a)lists.01.org" <opae(a)lists.01.org>
Subject: [OPAE] UDP parser
Message-ID: <cc68d7775d8048769d009252c1a5c8df(a)MX1.argela.com.tr>
Content-Type: text/plain; charset=3D"us-ascii"

Hi all

Hi all

I'm very new to Intel PAC (also RTL) and trying to figure out how to parse =
a UDP packet (plus payload) inside Intel Arria 10. I wanted to use this PAC=
 because the latency values are the best. I'll ask very basic questions for=
 you, so I apologize in advance.

1) There will be no switching between ports. The traffic is UDP Multicast, =
so ports just consume the network packets. I do not need to check VLAN, MPL=
S, IP options etc.. The UDP ports and payload are the same offsets, so with=
out a commertial hard or soft IP and UDP IPs, does it make sense just to do=
 with a PHY IP? What is the degree of difficulty, can I find any example?

2) I will need a PHY IP and Intel provides XAUI, 10 GBASE-R and Multi-rate =
PHYs. Also I will need DDRs IP for internal memory interface and PCEe? The =
AFU seems to handle these interfaces to connects to two banks of private DD=
R4-SDRAM memory and to the Intel Xeon processor through the CCI-P interface=
 and then the PCIe link. Does Intel provides them free, or do you need to p=
ay extra money for license?

3) Is there any TCP stack written in RTL (inside the AFU) or should I imple=
ment it by using CPU and Intel PAC together? Can you show a way about this?

Thanks in advance..

- Volkan



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