Re: [OPAE] Intel Fpga BBB Tutorial

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Because the MMIO address lines in the hardware don=E2=80=99t include the lo=
w 2 bits. The CCI-P spec. requires that they always be 0 since the minimum =
MMIO granularity is 4 bytes. The software and CPU do have those low 2 bits,=
 so the CPU-side computation differs by a factor of 4.

-Michael

From: OPAE <opae-bounces(a)lists.01.org> on behalf of Abel Eneyew <mul.abel=
43(a)gmail.com>
Date: Thursday, May 30, 2019 at 12:03 PM
To: "opae(a)lists.01.org" <opae(a)lists.01.org>
Subject: [OPAE] Intel Fpga BBB Tutorial

I am at the second part of the tutorial. But I am having difficulties under=
standing the mmio addressing part. Specificallly https://github.com/OPAE/in=
tel-fpga-bbb/blob/master/samples/tutorial/02_platform_ifc/02b_ccip_clock/sw=
/clock_freq_test.c#L226 why do we multiply the address by 4 but in the hard=
ware part  https://github.com/OPAE/intel-fpga-bbb/blob/master/samples/tutor=
ial/02_platform_ifc/02b_ccip_clock/hw/rtl/afu.sv#L150 it isn't multiplied. =
Why do we need to multiply it by 4 in the software part?

Sorry if this is not an interesting question. But I am new and it is confus=
ing.

Regards
Abel

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