Re: [PATCH] PCI: Disable NoSnoop and Relaxed ordering for Intel wireless BE200

On Thu, Jul 30, 2026 at 08:16:33PM +0000, Grumbach, Emmanuel wrote:
> On Thu, 2026-07-30 at 15:08 -0500, Bjorn Helgaas wrote:
> ...

> > I wonder if the PCI core should disable RO and NoSnoop on Root
> > Ports across the board?
> > 
> > I think this would mainly affect MMIO accesses performed by
> > drivers, and I suspect drivers expect those writes to be performed
> > in order, e.g., if the driver writes DMA descriptors to the device
> > followed by a write to a doorbell, those should stay in order.  If
> > the RP has RO enabled, those writes may be reordered.
> 
> As a device writer I'd say we'd be required to add a memory barrier
> in that case, but we use writel usually.
> Does that include a write vs write ordering? Hm...

Not being an ordering expert, I'm not sure I can make a convincing
argument for whether RO should be enabled or disabled for Root Ports.

Maybe it's easier to argue that whatever the RO setting is, it should
be the same across all platforms because drivers shouldn't have to
adapt to platform differences.

Root Port settings potentially affect several endpoints, and I think it
would be impractical for drivers to request RO settings that might
conflict with each other.

Do you have any visibility into whether and how other OSes actively
configure Root Port RO and NoSnoop across the board, independent of
individual drivers?