Re: [PATCH v17 03/14] KVM: arm64: Manage GCS access and registers for guests

On Fri, Jul 31, 2026 at 12:56:04PM +0000, [email protected] wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> - [High] GCS register context switch routines are incorrectly nested inside independent CPU feature checks (S1PIE and TCR2/TCRX), causing state corruption.

This was specifically requested by Marc on prior versions as GCS
architecturally depends on these features and it may improve code
generation.

> Is the GCS feature bit still explicitly masked out of the ID_AA64PFR1_EL1
> register limit?

> Looking at sanitise_id_aa64pfr1_el1() in arch/arm64/kvm/sys_regs.c, it appears
> the GCS bit is unconditionally cleared. If so, when the VMM tries to enable
> GCS via KVM_SET_ONE_REG, arm64_check_features() will validate against a limit
> of 0 and reject it with -E2BIG, making it impossible to expose GCS to guests.

This change is in the following enablement patch.

-----BEGIN PGP SIGNATURE-----

iQEzBAABCgAdFiEEreZoqmdXGLWf4p/qJNaLcl1Uh9AFAmpsvpQACgkQJNaLcl1U
h9D4DQf/RZLYi1M2kH9mqhRQuQZZsMuP6/nM+q2GwXMKIiYqekuu9cGnSbzj5em+
98EMlgO6DCzrO8dgby25rqrXF64D2NTJzsltMi3c3GKUaBEt/z2Ud8x72zSFSHpA
99NX2+rDIO5Lh5qXdWZAk+iyjuhRmn8acI7AITHqanoYBl63p0Us/6qFKX6uCzu3
gMJImEZh9FEfiMidHlfdMO6Hp0Xa7AmyQBNRlrFPkCm36lEyWKmAPBE5iyFsuCPs
vgSahIirRrgpTpPFh2r2q6gLNNC4bhDwG7Ptm+Eetxtv6KuQHc3sqgevbi7zfisf
/V2p8awwVaRg1gyB+VU7/FU1PUBuGg==
=R1lN
-----END PGP SIGNATURE-----